Thanku thanku sir, this is such a best teaching style. This helps me a lot. ur teaching style is amazing, .. please provide lecture on multi vivrational circuit.
thank you so much sir.the lecture was really helpful.can u please upload ur lectures on SIPO,PISO,PIPO,universal shift register,biderectional shift registers and buffer registers..it would really be of great help.
Finally, I can understand what Mumbo Jumbo is talking about when he says: "Just connect a D-FlipFlop to a falling edge monostable circuit"" while building a pumpkin farm
Mumbo Jumbo is a Minecraft youtuber. He mostly builds the so called "redstone" contraptions, which is basically a implementation of basic circuit elements inside the game. There are some people who made entire 8-Bit computers inside Minecraft
So basically we are considering in one clock cycle the time is enough only for the new input to pass through one flipflop such that the rest take the previous outputs as inputs and not the new one
First of all thnx sir.I am a student of IITI and your videos were of great help.The way you explained each topic with simplicity and to the point was great. Keep it on and thank you very much.
@Prateek Patel I am guessing because of the clock it will only take the value that is current. For example when d3 receives a input and d2 will also receive a input at the same time because its a synchronous circuit so at that when d3=1, q3 has a previous 0 which transfers over to d2
Thank u so much. Looks very simple when u teach.. Please make some more videos on ...minimization of specified sequential machines,partition techniques and merger chart methods-concept and minimum covertable.ASM- ssynthesis of output and state functions, data path,control path partition based designFault detection and locationI have seen almost all of ur videos of digital electronics and I bet no one can teach better than u. Pls pls make some more as soon as possible my exams are very near or provide me some good links.Thanku !
This reminds me on a project of years ago. It was used to create a audio echo with using serial shift registers. They called it a bucket line storage and used 8 bit wide and 1k long registers. The delay with running through those registers produced an echo effect.
🙏🙏🙏Thanks a lot sir🙏🙏🙏 Your videos are so helpful and useful during my university , I can't understand in online lecture and I don't attend it but I see Your all videos to study and I pass with good marks in my sem 3 university exam which is offline its because Your youtube channel and your extraaudinary teaching . Thanks a lot for making this videos and giving precious time us. -Thanks a lot -God bless you ..sir -I don't have words to express thankfullness to you Your youtube channel is an individual university. Thanks a lot for helping us 🙏🙏🙏🙏🙏
good presentation of the concept thanks for the input., and finally learnt the meaning behind the concept of connecting a D-flip flop to a falling a edge monostable circuit cuz ot has been a pain to understand the fundamentals behind it for the last 2 months for me! great vid!!
maybe because it is negative edge triggered flip flops that we are using, so the q3 changes only at the negative edge since Din=1 but at the time of clock change q3 is still 0 so there's no reason for the q2 to change as q3 changes just after the clock change
Because it is negative edge triggered not negative level triggered. So D2 has to wait for the negative negative edge to change its value. What I meant is that value of D2 won't change until the next clk pulse.
Well it's because of clock and I its think already explained by people below but keep in mind that dont state the reason of d2 to being 0 by stating that clk is negative edges/level triggered in exams because you can keep it positive as well , would work just the same but the graph would differ .
CONFUSION......3:09 you have said that "I have already written the outputs before giving the inputs which are 0,0,0,0". Now when input was given to D3 ie D3=1, even after that you have taken D2=0 as Q3 was equal to 0, but you have given input 1 then Q3 would be equal to 1.....plz explain it
I was wondering when D(3) is 1 Then Q(3) is 1 , then why (D2) is not equal to 1 and that results in Q(2) is equal to 1 and similarly (Q0) is equal to 1 instantenously as these are all are connected?? why the value of Q2 or Q1 or Q0 changes only when second or third is provided to D3.
This happens due to delay of gates present in D-flip flop which is higher than delay caused by clk(which is a single wire).By the time o/p 1(high) of Q3 for LSB reaches D2 the clk pluse turns zero so it doesn't counts. Initially Q-3,2,1,0 are 0. When the first negative edge of clk simultaneously arrives at all input side, input at D3 at that time is 1 at D2 is 0 at D1 is 0 at D0 is 0. Same goes further cases. Hope this helps.
Thank you so much for clarification, I did thought may be it was because of master slave relation where on first it gets stored and on second pulse it shift. How wrong I was and I asked the same thing to many my friends but now I realize they have all wrong concept of it. Now it solves all and fit perfectly to puzzle. And By the way thank you so much for such nice lessons..It has helped to an enormous extent, whenever Teacher teache us and I have no idea what he is teaching....your channel always comes in my mind and take away all worries and when I came back you don't disappoint me too....Thanks one again.
Thanks for the explanation but I have a question. Do we really need only N clocks for an N bit SISO register? Since we are tapping the output only at the end. Someone help me understand better
9:31 but to get the entire output of 1111 shifted out we would need eight clock pulses right? Because we can only see Q0 as the output then after 4 clock pulses the o/p would be 1 but as we go from 4 to 8 pulses we would get 1,1,1,1 as the o/p of Q0.
It could be my misunderstanding , But doesn't it seems to be a parallel output because serial output is made of more than one bit. please someone correct me.
Late reply but might be helpful for others: The above video gives parallel output only, if you observe Q0 then you will see that after 4 pulses, it contains only the LSB, so you need to give another 3 pulses to shift the remaining bits to Q0.
@@prasanjitrath281 Right! I just checked again and found that even if we give 3clock pulses extra, the data we're getting in serial form is in reverse order. I took 1011 as an example, the order I got is in reverse. Please clarify.😐
@@AnoNymous-po5sx That is happening because you are feeding the left most bit first to register, so you are getting 1101 for 1011 input. So, if consider your example as 1011, just start feeding the MSB first and then go towards LSB.
thaaaaank you very very very very very very very very very very very very very very very very very very very very very very mmuuuch , I got an " A " and you course was helpful
In case you have nt got the ans., still.....That is Din as in the input , in the subsequent lecture he had told that its a good practice to raise it before the negative edge just for the initial inputs(not for Q0, Q1, Q2, Q3) .That is how the system literally works.
This happens due to delay of gates present in D-flip flop which is higher than delay caused by clk(which is a single wire).By the time o/p 1(high) of Q3 for LSB reaches D2 the clk pluse turns zero so it doesn't counts. Initially Q-3,2,1,0 are 0. When the first negative edge of clk simultaneously arrives at all input side, input at D3 at that time is 1 at D2 is 0 at D1 is 0 at D0 is 0. Same goes further cases. Hope this helps.
The clock line enters the D- Flip flop with an arrow head. The arrow head means the FF is negative edge triggered, if there is no arrow the FF is positive edge triggered.
I need to know how to solve this kind of problems as soon as possible Sir, - You have an 8 GB RAM module with 8 byte words. Calculate: The number of locations in the RAM module. The number of address lines in the RAM module. - Given that the RAM is constructed from 4K X 16 bit RAM chips, calculate: The number of chips needed. The number of address lines that need to be connected to the 4K X 16 RAM chips. The number of address lines that need to be connected to the decoder. The size of the decoder required.
No you cant upload the msb first at right shift register only at left that why you example is not convenient you should have use "0011""0101" for better understanding
costpsy To upload data using msb you need to reverse the outpur ports..that is q3 to q0, q2 to q1, q1 to q2 and q0 to q3. where q3 is msb and q0 is lsb.
the funny thing that made me laugh ... i openned power point for my prof. i found him putting screens of neso acadmy videos 😂 🤣
🤣🤣🤣
@@electronicengineering6035 lol
your prof belike:- send me the playlist's link, i need this
Hanwate
Broo same xddd
Simple lectures though powerful teaching💯🔥... whomever have some doubts prefer Neso academy that's ur power💪❤️
These videos are simply excellent for students, hobbyists and all those who keep learning for a lifetime !
My teacher completely skipped the sequential logic circuits just because its hard!
Your videos have helped me so much!
I really appreciate it!
same here🙂
I joined in a core company. Company told me to watch Neso academy videos for learning
This channel is life saver for enginering students...
Sir, you sure have a great talent for teaching.thank you!
U will always be in my prayers.. Thank you so much for helping me out with the concepts..
best teaching channel in youtube❤️ totally love the way these ppl teach.
Thanku thanku sir, this is such a best teaching style. This helps me a lot. ur teaching style is amazing, ..
please provide lecture on multi vivrational circuit.
you saved my finals 😭😭
thank you so much sir.the lecture was really helpful.can u please upload ur lectures on SIPO,PISO,PIPO,universal shift register,biderectional shift registers and buffer registers..it would really be of great help.
Finally, I can understand what Mumbo Jumbo is talking about when he says: "Just connect a D-FlipFlop to a falling edge monostable circuit"" while building a pumpkin farm
What reference is that buddy?
Mumbo Jumbo is a Minecraft youtuber. He mostly builds the so called "redstone" contraptions, which is basically a implementation of basic circuit elements inside the game. There are some people who made entire 8-Bit computers inside Minecraft
@@sergejkeser7270 thanks dude
@@sergejkeser7270 what is the need for a D flip flop to build a pumpkin farm?Can u share me the video :)
@Prateek 🅥 see the truth table
Thanks for this awesome lecture sir..the only reason i got good grades in my digital electronics course is due to neso academy
better teaching than my prof..thanks a lot
marhsall 27777 how dare you compare this GOD to your prof
@@rohanram7197 Really This channel more helpful in this subject than my University in Europe
before sem NETFLIX while sem NESO 🥶🥶
Which clg?
@@sadiqyt7664 IIT Dhanbad
my sir just tell steps but after watching your video I actually know the reason behind the concept what and why we do ...thank you so much sir
Awesome Sir, we a
Only knew, we have to do *right shift* , but why we do this, today you explained,... So lucky to have this video during my session.
Thank you for helping the students from your unique and wonderful teaching and clearing the concepts ☺
Explanation was great.. But You should have made separate TABLE FOR D3,D2,D1,D0..
(For better understanding)
true
So basically we are considering in one clock cycle the time is enough only for the new input to pass through one flipflop such that the rest take the previous outputs as inputs and not the new one
I am really grateful to you sir. Your lectures helped me a lot to understand Digital Electronics. Thank you : )
First of all thnx sir.I am a student of IITI and your videos were of great help.The way you explained each topic with simplicity and to the point was great.
Keep it on and thank you very much.
the quality of video is less but the quality of content is epic!
your lessons helped me greatly in exam,thanks.
Neso Academy provided the best tutorails ,good explanation
thank u vvvv eee rrr yyy much
Amazing video! Really helping me study for me ECE midterm right now
@Prateek Patel I am guessing because of the clock it will only take the value that is current. For example when d3 receives a input and d2 will also receive a input at the same time because its a synchronous circuit so at that when d3=1, q3 has a previous 0 which transfers over to d2
Thank u so much. Looks very simple when u teach.. Please make some more videos on ...minimization of specified sequential machines,partition techniques and merger chart methods-concept and minimum covertable.ASM- ssynthesis of output and state functions, data path,control path partition based designFault detection and locationI have seen almost all of ur videos of digital electronics and I bet no one can teach better than u. Pls pls make some more as soon as possible my exams are very near or provide me some good links.Thanku !
This reminds me on a project of years ago. It was used to create a audio echo with using serial shift registers. They called it a bucket line storage and used 8 bit wide and 1k long registers. The delay with running through those registers produced an echo effect.
This was the most boaring subject for me.But because of u I m enjoying this subject now.Thnku sir u and ur way of teaching are just wonderful :-):-)
Amaaazingggg🤩
But if you give notes also in a link or something 😅😅
Hoy la academia de Neso me dio una gran introducción para mi conferencia. Gracias👌
i am really gratefull sir. you have made my life easier. thank you
*VERYYY NICE EXPLANATION IN UA-cam ONLY ON THIS VIDEO 😇😇😇😇VERY NICE TEACHING METHODS 👌🏻👍🏻🔥🔥🔥TYSM😊*
So, for left shift we need to give Din to FF0 and take serial out from FF3
🙏🙏🙏Thanks a lot sir🙏🙏🙏
Your videos are so helpful and useful during my university , I can't understand in online lecture and I don't attend it but I see Your all videos to study and I pass with good marks in my sem 3 university exam which is offline its because Your youtube channel and your extraaudinary teaching .
Thanks a lot for making this videos and giving precious time us.
-Thanks a lot
-God bless you ..sir
-I don't have words to express thankfullness to you
Your youtube channel is an individual university.
Thanks a lot for helping us
🙏🙏🙏🙏🙏
Love you sir....you give us beautiful lectures😇😇😇
i most like your speech and clear thoughts about any topics . thank you for providing this.
excellent teaching.....everyone can understand easily....
MUKESH KUMAR BADIGINENI you don’t get to decide that
good presentation of the concept thanks for the input., and finally learnt the meaning behind the concept of connecting a D-flip flop to a falling a edge monostable circuit cuz ot has been a pain to understand the fundamentals behind it for the last 2 months for me! great vid!!
How did he draw the time sequence for Din..
hows d2 = 0 in the first case because the q3 is the input for the second d flip flop
Exactly...
Because of clk
maybe because it is negative edge triggered flip flops that we are using, so the q3 changes only at the negative edge since Din=1 but at the time of clock change q3 is still 0 so there's no reason for the q2 to change as q3 changes just after the clock change
Because it is negative edge triggered not negative level triggered. So D2 has to wait for the negative negative edge to change its value.
What I meant is that value of D2 won't change until the next clk pulse.
Well it's because of clock and I its think already explained by people below but keep in mind that dont state the reason of d2 to being 0 by stating that clk is negative edges/level triggered in exams because you can keep it positive as well , would work just the same but the graph would differ .
You make every concept very easy. Thank you Sir
U have abolish my huge unconscious doubt, thanks.
So comfortable , so professional.
CONFUSION......3:09 you have said that "I have already written the outputs before giving the inputs which are 0,0,0,0".
Now when input was given to D3 ie D3=1, even after that you have taken D2=0 as Q3 was equal to 0, but you have given input 1 then Q3 would be equal to 1.....plz explain it
please someone answer this +1
Good job.Ur an inspiration for ec brothers. Welcome to ktu.Roll back year back
Ec brothers😍
I was wondering when D(3) is 1 Then Q(3) is 1 , then why (D2) is not equal to 1 and that results in Q(2) is equal to 1 and similarly (Q0) is equal to 1 instantenously as these are all are connected?? why the value of Q2 or Q1 or Q0 changes only when second or third is provided to D3.
This happens due to delay of gates present in D-flip flop which is higher than delay caused by clk(which is a single wire).By the time o/p 1(high) of Q3 for LSB reaches D2 the clk pluse turns zero so it doesn't counts. Initially Q-3,2,1,0 are 0. When the first negative edge of clk simultaneously arrives at all input side, input at D3 at that time is 1 at D2 is 0 at D1 is 0 at D0 is 0. Same goes further cases.
Hope this helps.
Thank you so much for clarification, I did thought may be it was because of master slave relation where on first it gets stored and on second pulse it shift. How wrong I was and I asked the same thing to many my friends but now I realize they have all wrong concept of it. Now it solves all and fit perfectly to puzzle. And By the way thank you so much for such nice lessons..It has helped to an enormous extent, whenever Teacher teache us and I have no idea what he is teaching....your channel always comes in my mind and take away all worries and when I came back you don't disappoint me too....Thanks one again.
downside up! Thank u bro
@@vinamra4893 where did you learn this bro?
@@vinamra4893Yaaa
Thanks for the explanation but I have a question. Do we really need only N clocks for an N bit SISO register? Since we are tapping the output only at the end. Someone help me understand better
Actually 2n-1 clock pulses are required as we are taking the output at the end
9:31 but to get the entire output of 1111 shifted out we would need eight clock pulses right? Because we can only see Q0 as the output then after 4 clock pulses the o/p would be 1 but as we go from 4 to 8 pulses we would get 1,1,1,1 as the o/p of Q0.
I think we'll need 7 clock, actually for n FFs, we need n clock for storing i/p, and (n-1) for taking o/p. So, total will be 2n-1
Honestly speaking just because of only you I passed my exam
YOU ARE A GREAT TEACHER, THANKS TO YOU I GET 100 POINTS FROM MY LOGIC MIDTERM AND WENT TO THE OBJECTION.
This was just perfect by you sir!
Thank u so much sir...you explained it very well....finally i understood..😅
Very nice teaching sir!!!!
Siso output is take last flipflop. Q0. So after four clock pulse again 3 clock added. We get out/p is at Q0
u are my sifu thanks for sharing☺️
Excellent Teaching ...... Tq
Why do you always take a negative edge clock, any specific reason?
Plz... make videos on Analog To Digital Converter and Digital To Analog Converter
Interesting topic sire
You have written output in parallel
Thanks a lot for telling lsb would go first... my teacher confused me by using palindromes. E.g. 1001 and 101101🙂
And he told me msb would go first...
Usually the most adjacent flipflop is the lsb but in registers the output from that flipflop is taken as msb why?
It could be my misunderstanding , But doesn't it seems to be a parallel output because serial output is made of more than one bit.
please someone correct me.
Late reply but might be helpful for others: The above video gives parallel output only, if you observe Q0 then you will see that after 4 pulses, it contains only the LSB, so you need to give another 3 pulses to shift the remaining bits to Q0.
@@prasanjitrath281 Right!
I just checked again and found that even if we give 3clock pulses extra, the data we're getting in serial form is in reverse order. I took 1011 as an example, the order I got is in reverse. Please clarify.😐
@@AnoNymous-po5sx That is happening because you are feeding the left most bit first to register, so you are getting 1101 for 1011 input. So, if consider your example as 1011, just start feeding the MSB first and then go towards LSB.
@@prasanjitrath281 Yeah I got it. Thank you! 😁😁😁
sir then what about load and clear as you told in previous lecture
thaaaaank you very very very very very very very very very very very very very very very very very very very very very very mmuuuch , I got an " A " and you course was helpful
DEC is so easy,thanks to you.
Sir What about Shift control registerS? Do you have any lecture on this topic?
Thank you so so much for this video.
Your teaching skill is excellent.
thank u so much , very good tutorial , keep on posting like this.
You are amazing , thank you !
Having my exam tomorrow
Hi. Can you pls make some videos on Serial Receivers for digital logic? I dont know how to design them or the concept. Ty!
Sir can you please tell me why the clock is set down in the table?
thank you very much
At 7:24 why didn't u rise at the negative edge?
In case you have nt got the ans., still.....That is Din as in the input , in the subsequent lecture he had told that its a good practice to raise it before the negative edge just for the initial inputs(not for Q0, Q1, Q2, Q3) .That is how the system literally works.
Thanks for your presentation. It would be better to understand if you use input with the same bit. For example, 1010
Sir I have one doubt. can we use positive clk pulse or not
Why D becomes 1 in the middle of the clock pulse?
Very nice video 👌 it helpful for me
Nice presentation, clearest shift-register demo I've ever seen.
thank you sir you have saved me
IF D3 is given as 1, shouldnt the output, i.e Q4 be iving out 1? why is it 0?
please help.
This happens due to delay of gates present in D-flip flop which is higher than delay caused by clk(which is a single wire).By the time o/p 1(high) of Q3 for LSB reaches D2 the clk pluse turns zero so it doesn't counts. Initially Q-3,2,1,0 are 0. When the first negative edge of clk simultaneously arrives at all input side, input at D3 at that time is 1 at D2 is 0 at D1 is 0 at D0 is 0. Same goes further cases.
Hope this helps.
Tutorials definitely okay for SISO
Why we have to give negative edge triggered Clock input
please give the link to previous and next video in the description
There is an explanation to why you use falling edge activated FF's?
Yes plese explain...
why are u particularly considering "negative edge triggering"?
The clock line enters the D- Flip flop with an arrow head. The arrow head means the FF is negative edge triggered, if there is no arrow the FF is positive edge triggered.
@@khalidhindi2320 The circle before the arrow indicates falling edge sensitive. The arrow indicates a synchronous clock.
sir please provide set of typical question too
thanks
I need to know how to solve this kind of problems as soon as possible Sir,
- You have an 8 GB RAM module with 8 byte words. Calculate:
The number of locations in the RAM module.
The number of address lines in the RAM module.
- Given that the RAM is constructed from 4K X 16 bit RAM chips, calculate:
The number of chips needed.
The number of address lines that need to be connected to the 4K X 16 RAM chips.
The number of address lines that need to be connected to the decoder.
The size of the decoder required.
Sir what is the meaning of downward arrow ??? In truth table...
negative edge trigerring
(falling edge of the clock)
I am confused as you are taking input and output before operating the register then again taking it after the operation
No you cant upload the msb first at right shift register only at left that why you example is not convenient you should have use "0011""0101" for better understanding
costpsy To upload data using msb you need to reverse the outpur ports..that is q3 to q0, q2 to q1, q1 to q2 and q0 to q3. where q3 is msb and q0 is lsb.
but in the next presentaion he hs used q3 as lsb.... so which one to follow
"What I have to do?" vs. "What do I have to do?", the latter is correct.
I have a doubt sir.. Why do you always put negative edge triggered clock there?
because positive edge triggered clock make FF races , which is not desirable , especially in JK FF
@@manaveshnarendra4163 Thanks😄 but my exam is over 😂
@@nannubedi7773 🤣🤣🤣
Hi Neso, what happends if not all bits you want to store is the same, for example "1010" ?
Thanks for your Teaching ,It Is very smart and great
but i have a question IS it support shifting any number in 4-bits for example 1100 ?
So this kind of register doesn't storage any data, it only receives data and sends that data.
Serial output is taken from the Q0 then taking output at every negative edge it will be 1000 so output is not correct. Isn't it?