10:26 but over here where is the output line, even we make it out of Q0 we will have the LSB bit always as an output intill EN is high again tnx for videos
Yes, if Q0 is the only output line, then until EN is high, the output will be Q0. Typically in many shift registers, there is a provision to get all the bits as an output (to get parallel output from all the bits of the shift registers)
At 6:14, when you show the graphical output, I don't understand why the inputs change on every negative edge of the clock pulse. Is that an error? It should have coincided with every POSITIVE edge, right? Please clairify! P.S., love your videos!
Input is bit stream which we want to feed into shift register. It is not necessary that, it should follow the clock signal. It can change independent of clock signal. But the shift register will respond to that input at the rising edge of the clock. I hope, it will clear your doubt. If you still have any doubt then let me know here.
in bidirectional register there is no enable input so after loading the data into the register how can we make sure there is no random input present in the input
Typically, it has to be there. But if it not there then you can use additional external logic, like you can disable the clock, so that once you write the data, no additional data can be written into register.
@@ALLABOUTELECTRONICS ok no problem, can you make playlist from basics in Hindi. I mean new series for Hindi or hindi English. For Hindi viewers. I think it will helpful for both Hindi and English viewers , also for viewers who don't known English or may bi Hindi properly. Well I am one of them. sir I request to you ,if you are comfortable. Thanks for replying my comment sir . Good day.
The timing diagram shows how the output of the each flip-flop in the shift register changes with every clock pulse. At the rising edge of the clock, whatever input that is present in front of each flip-flop (in this case, that is the output of the previous stage), it will be loaded in the flip-flop. The Q3 or the MSB of the shift register will follow the serial input at the every clock pulse. Q2 will follow the output of the Q3 at the every rising edge. And the same is the case of Q1 and Q0. Now, if you see the timing diagram then you can understand it easily. Here the outputs Q3, Q2, Q1 and Q0 of the flip-flops have been slightly shown delayed due to the propagation delay of each flip-flop. I hope, it will clear your doubt.
For more videos on Digital Electronics, check this playlist:
bit.ly/31gBwMa
Wish we had teachers like you in our colleges!!
our teacher also explains things in good manner but i missed this topic.
best explanation on shift registers👌🏻👌🏻👍🏻
Really very nice 👍👍
10:26 but over here where is the output line, even we make it out of Q0 we will have the LSB bit always as an output intill EN is high again tnx for videos
Yes, if Q0 is the only output line, then until EN is high, the output will be Q0.
Typically in many shift registers, there is a provision to get all the bits as an output (to get parallel output from all the bits of the shift registers)
At 6:14, when you show the graphical output, I don't understand why the inputs change on every negative edge of the clock pulse. Is that an error? It should have coincided with every POSITIVE edge, right? Please clairify! P.S., love your videos!
Input is bit stream which we want to feed into shift register. It is not necessary that, it should follow the clock signal. It can change independent of clock signal. But the shift register will respond to that input at the rising edge of the clock. I hope, it will clear your doubt. If you still have any doubt then let me know here.
Ahh got it, thanks a million!
V. Nice Continue 👍
Very nice 👌👌👌👌
Thank you ❤️
GOOD explanation
very nice 👍👍
Sir, what is the application and use of the siso in our digital logic design?
can you say which software u using?
in bidirectional register there is no enable input so after loading the data into the register how can we make sure there is no random input present in the input
Typically, it has to be there. But if it not there then you can use additional external logic, like you can disable the clock, so that once you write the data, no additional data can be written into register.
Once again explain sir
i think u confuse its not SISO SIR. Its bidirectional shift register. for siso we need 8 clock pulses
For a SISO register of N-bits, to shift the N-bit data we require N clock pulses. The bi-directional shift register is covered from 13:10 onward.
Please make videos in Hindi as well sir.
Some time back, I have asked for the same to the viewers and have done the poll. But most of them ( more than 85%) wants the videos in English.
@@ALLABOUTELECTRONICS ok no problem, can you make playlist from basics in Hindi. I mean new series for Hindi or hindi English. For Hindi viewers. I think it will helpful for both Hindi and English viewers , also for viewers who don't known English or may bi Hindi properly. Well I am one of them. sir I request to you ,if you are comfortable. Thanks for replying my comment sir . Good day.
I can't understand timing diagram sir
The timing diagram shows how the output of the each flip-flop in the shift register changes with every clock pulse. At the rising edge of the clock, whatever input that is present in front of each flip-flop (in this case, that is the output of the previous stage), it will be loaded in the flip-flop.
The Q3 or the MSB of the shift register will follow the serial input at the every clock pulse.
Q2 will follow the output of the Q3 at the every rising edge. And the same is the case of Q1 and Q0.
Now, if you see the timing diagram then you can understand it easily. Here the outputs Q3, Q2, Q1 and Q0 of the flip-flops have been slightly shown delayed due to the propagation delay of each flip-flop.
I hope, it will clear your doubt.
Thank you🥰