Q. why resistive inverter is not used? a. actually resistive inverter is not simple as we see in circuit diagram. we design the resistance value within the piece of semiconductor only. So a large amount of area is used in comparison to cmos inverter. The dc power dissipation in cmos inverter is negligible and the Voltage transfer curve of Cmos inverter is almost like the VTC of ideal inverter(i.e the slope around the tripping point is almost infinity) but in resistive inverter the VTC has a finite slope in between VIL and VIH.
Q. What will happen if we interchange the PMOS and NMOS?? Ans ( I think ): It will be a Poor buffer with reduced VOH and increased VOL. It is not an inverter. We don't use this buffer because the reduced levels can create a lot of disadvantages ( in the next stage output, Power consumption, etc. ).
@@whyRD and sir keep on adding such valuable content regarding logical , conceptual questions and any other notes or content related to vlsi and digital subjects...since we follow u strongly
Q. what happens if we interchange the pmos and nmos? Ans: yes it is still an inverter but we donot get rail to rail swing at the output, so we this configuration is not used.
Really appreciate your content!! Can Diploma (E&C) holders enter into VLSI field? Will the companies hire Diploma Engineers for VLSI field? Do you have any suggestions to overcome this issue.
Please change the background from grey to white
Q. why resistive inverter is not used?
a. actually resistive inverter is not simple as we see in circuit diagram. we design the resistance value within the piece of semiconductor only. So a large amount of area is used in comparison to cmos inverter. The dc power dissipation in cmos inverter is negligible and the Voltage transfer curve of Cmos inverter is almost like the VTC of ideal inverter(i.e the slope around the tripping point is almost infinity) but in resistive inverter the VTC has a finite slope in between VIL and VIH.
Bhai kab 22 minutes ho gaye pata hi nahi chala maza aa gaya ❤
wow , this comment makes my day . Thanks for your time brother
Great my big brother. This is very helpful for people who need some example to get started and going. Thanks a lot.
Thanks a lot for this initiative sir...much love 😇❤️
Great Initiative Kindly continue like this and cover some topics on physical design also.
Static timing analysis would be great..!
I really appreciate your effort sir, the mission on spreading the knowledge on VLSI
Q. What will happen if we interchange the PMOS and NMOS??
Ans ( I think ): It will be a Poor buffer with reduced VOH and increased VOL. It is not an inverter. We don't use this buffer because the reduced levels can create a lot of disadvantages ( in the next stage output, Power consumption, etc. ).
It is a very good start, hoping many videos like this.
yes sure , already 7 episode are out
Splendid work 👍
great initiative sir. thank you
very informative, keep it up.
Thank you for sharing your knowledge. Keep it up👍
Thank you so much for the playlist.
Nice bro , do videos on how to use eda tools like quartus prime also if possible
Great sir👍🏻
Excellent
Great explanation sir , Thank you !!
Most welcome!
Please Try to make a video for :-
Why PMOS Bulk/Substrate connected with VDD/Source?
And aslo why NMOS Bulk/Substrate connected with gnd?
Important topic will stress on this topic for sure
Thank you for your efforts
Great vdo bro ❤️ Thanks a lot..
Sir use different color it's not visible properly
Let me see
@@whyRD and sir keep on adding such valuable content regarding logical , conceptual questions and any other notes or content related to vlsi and digital subjects...since we follow u strongly
will do
Can you make videos on scaling and sizing
Thank you
Really Enjoy watching your video and learning all detail stuff. Thanks for making such good content
thank you sir
When we interchange nmos and pmos in cmos inverter it will act as a buffer with degraded high and low voltage levels
How is ltspice to make pmos and nmos related projects for interview??
sir please use dark background and light colour when you are explaining, pls don't use red colour sir.
Thanks for this geed back will follow this
@@whyRD white and black would be great😊
White background, I am not sure as it cause strain to your eyes.... Will experiment around
@@whyRD black bg and white ink
Nmos logic suffers from power dissipation all the time .
As well it is ratioed logic
perfect 🙂
@@whyRD thanks sir 😀
Q. what happens if we interchange the pmos and nmos?
Ans: yes it is still an inverter but we donot get rail to rail swing at the output, so we this configuration is not used.
Why it's so important to have rail to rail swing?
@@whyRD so that we get better noise margin levels??
After interchanging it will be buffer correct?
@@pika4803 nope. it will remain as inverter but the performane will be low?
@@anonymous-fp9og no it will not work as an inverter in exchange case
❤️
Can a B.E(Electrical and electronics engineering) get job as Fresher in VLSI with All Capabilities??pls
Yes
Really appreciate your content!! Can Diploma (E&C) holders enter into VLSI field? Will the companies hire Diploma Engineers for VLSI field? Do you have any suggestions to overcome this issue.
Hi vinayak,
Yes Diploma candidates can enter VLSI field. Companies Iike moschip hire diploma people for analog layout engineers.
You can apply vedaiit exams
🤌simply awesome
Change the Background please
done for Ep2 chk out
when will the new video come?
on or before tomorrow 8pm , trying my best to bring min 2 video each week
@@whyRD Thank you sir
Thank you sir for this effort