Synthesis/STA - Half cycle path setup and hold timing

[@pavankumarreddy7888]

I think hold slack will be increased by T/2 for Half cylce path compared to full cylce path

[@VLSI-learnings]

frequency changes will not effect the hold .

[@arunkumar-xl3vl]

Good Explanation sir, For suppose ifn1st flop is -ve triggered and second flop is +ve triggered then is these possible to find half cycle path

[@VLSI-learnings]

Thank you

[@likhithareddy2165]

Can u explain more topics on STA like DRV violation,lockup latch,skew useful skew and more

[@VLSI-learnings]

i dont have about that

[@gumsraju1957]

Hi,
Can you please take one session on how hold is Independ of frequency..Subscribed and waiting for video

[@meetipatel6259]

Hi Nice video, can you please explain why hold benefits by half cycle when Launch clock is positive edge triggered and capture clock is negative edge triggered

[@VLSI-learnings]

Thanks you

[@mahaboobpeershaik658]

for t_hold no change in hold equation
But for t_hold >= T_clk/2 then
--> t_hold

[@mvm289]

Sir could you please explain,will hold violations occur in half cycle path ? If yes why they occur?

[@Narennmallya]

Nice explanation.
Could we also have a quarter cycle path? wherein capture ff has frequency f (maybe 200Mhz) along with an inverted logic at clock pin and launch flop at f/2(same example 100 Mhz)

[@manumk8672]

Nice , very simple explanation ! Give us more details about sta concepts and constraints

[@VLSI-learnings]

Thanks, will do!

[@madhugowda303]

Your explanation is good but you forgot main things that is where we need to check setup and hold in half cycle paths

[@VLSI-learnings]

ok tell me . where i missed it .

[@jithinkjoy7789]

I Think for half cycle and multicycle paths....hold is frequency dependent.......Please check it

[@VLSI-learnings]

simple example . my design is working in 500 mhz then i changed my design 750 mhz . then setup will effect or hold will effect .

[@coastalfly5508]

Hold is independent of frequency.. It's depends on Arrival time delay..

[@mikewang9191]

Hold has NO role to play in frequency of the design as long as it is a FULL cycle path. Frequency has a role to play in half-cycle paths/clock gating checks and this presentation is misleading. Please use a PrimeTime session to see results for yourself. But the presentation is a bit misleading as it fails to give full context

[@dSparc]

Hold for half cycle path is Tpd + Tclk_period/2 > Thold. So there is clock frequency at play. As someone suggested look at Prime Time timing reports and correct the mistake. In the case of half-cycle paths, hold is not an issue because you are adding half a clock-cyle path to a typical 0 cycle-path hold timing calculation

[@GK-yr7sx]

Clear explanation for half cycle path

[@VLSI-learnings]

thank you

[@srilakshmipeteti8087]

thank you so much explained very clearly

[@VLSI-learnings]

Thank you

[@413sekharece]

Where there are used in real time application

[@VLSI-learnings]

i explained in the video those are two real time example only

[@413sekharece]

@@VLSI-learnings ok

[@kasimkhan5352]

Hi sir, Nice explanation.
Can you please also explain multi cycle path .

[@VLSI-learnings]

Ok 👍

[@khurashiasif1164]

nice explanation

[@VLSI-learnings]

thank you

[@saikumarganaparapu8496]

Sir please upload more problems on setup and hold

[@VLSI-learnings]

ua-cam.com/video/GFcjHo_AH0o/v-deo.html
ua-cam.com/video/xEtPa_6B4SI/v-deo.html
go through this links you will get setup and hold information

[@rohanyadala9096]

U r super sri

[@yesubabuakunuru8117]

How to solve hold and setup violations

[@VLSI-learnings]

ua-cam.com/video/xEtPa_6B4SI/v-deo.html go to this link

[@rajenderreddy5657]

Super

[@VLSI-learnings]

Thank you

[@dw008cts5]

What you are telling is absolutely wrong. For half cycle paths hold check becomes relaxed by half cycle and for half cycle paths hold becomes frequency dependent. Please get your own concepts clear before teaching.