On-Chip Capacitors (MiM, MoM, PiP, Mos Varactor)

[@rajathmvenugopal8313]

The practical examples which you take make the videos more engaging, thanks a ton for your hard work sir

[@analoglayoutdesign2342]

thanks for the feedback.

[@vinaycrasta7459]

Have watched couple of videos in this channel and got to learn a lot. Thank you Sir!!!

[@yassinet.benchekroun5087]

Thank you very much for your efforts in making this. Very helpful!

[@analoglayoutdesign2342]

Thanks for the feedback

[@sivasankaransc3384]

you are doing great work!. Thanks a lot!!!.

[@someshprajapati4474]

Nice explanation,in general vlsi design engineer should know all about this.

[@koppulapeter8720]

Keep up the good work sir

[@張鈞堯-h4m]

Thank you very much!!!
Always learn a lot.

[@dallasjohnson6060]

you are awesome! Its hard to find good videos on IC design. Keep it up!

[@analoglayoutdesign2342]

thanks for your feedback.

[@durgasubrahmanyam2138]

way of explanation is good

[@analoglayoutdesign2342]

Ok thanks

[@asha503]

Nicely explained 👌

[@varshakamat789]

Hi Sir. Your explanations are really good. Thank you for the videos.
Sir, I have the below question
Can we use a combination of Poly and Metal caps for Decaps?

[@analoglayoutdesign2342]

Yes I think, if DRC permits.i think you are speaking about double poly, pip cap and then mom cap.. generally it's mos cap + mom cap...

[@kshitijsingh636]

Thanks for this informative video sir🙏Please make a video on Desity issues and need of custom fills (metal/base) from design perpective.Thanks

[@bhavanavalaboju6098]

Hi sir, thank you for the useful content. Consider APmom capacitor using 22nm fdsoi.
a) I increased the oxide width from 1u to 1.033u, the cap remained same with 11 fingers (the device is automatically taking the number if fingers as 11).
b) But when i increased the width to 1.034u, the cap increased and the number of fingers automatically increased to 12.
Doubt: what changed during a) such that the cap value remained the same. Thanks a lot.

[@analoglayoutdesign2342]

In case a, you only increased the width of insulator. Not the thickness. If you had increased the thickness of insulator, then cap would have decreased. But it’s a process thing and you can’t increase insulator thickness. Width of the insulator will not have effect on cap value.
In case b, you changed the metal width, now cap has to change and it did.
Hope this clarifies

[@bhavanavalaboju6098]

@@analoglayoutdesign2342 Thank you for the response sir.
But in a) as the width of the oxide increases, the area of the metal that holds the oxide in between also increases.(The number of fingers are 11 by default). This should increase the cap.
In b) I did not increase the metal width, I just increased the width of oxide from 1.033u to 1.034u (which increased the number of fingers to 12 automatically).
I do not understand what exactly happened with the cap when the width of the oxide is increased from 1.033u to 1.034u

[@analoglayoutdesign2342]

So, the cap is fixed till number of fingers are same. That’s may be manufacturing accuracy. You may check the extracted netlist cap. May be that will change when you increase width of oxide without increasing the fingers

[@bhavanavalaboju6098]

@@analoglayoutdesign2342 okay, thank you.

[@anujshah4909]

Can you please make a video on Decoupling capacitors? e.g how on-die and off-die capacitor will help?

[@analoglayoutdesign2342]

Yes sure.. will do that when I get time

[@karthikmaheshrao6021]

Voltage coefficient mainly depends on the form factor of the capacitors. Bigger the form factor better the voltage coefficient behaviour.

[@analoglayoutdesign2342]

Thanks for the additional information

[@anilkumarpattapu4309]

Which cap has more fabrication steps mim or mom?

[@analoglayoutdesign2342]

MiM uses separate metal layer…
MoM uses existing metal layers only

[@anilkumarpattapu4309]

@@analoglayoutdesign2342 thanks yes i got this so as mom has more metal layers and inbetween oxide mom has more fabrication steps bcz mim has only one extra layer which is ctm

[@timegogo4182]

Thank you Sir🙏

[@meghachandargi6805]

Thank you so much sir

[@shanejohns7901]

@3:01 "No real capacitor is loss less but an ideal one is and some real ones almost are."

[@analoglayoutdesign2342]

Lossless, I meant , as compared to resistor.. of course there will be losses bcos of parasitic resistance… still it can be efficient

[@sharathseshadri3698]

Can you explain antenna in MIM cap

[@satishvasamsetti2399]

Small question .....why we will maintain minimum and maximum metal density ...plz answer me sir

[@analoglayoutdesign2342]

Density rules are to do with mechanical part of the IC design..

[@satishvasamsetti2399]

@@analoglayoutdesign2342 u mean cmp ?

[@analoglayoutdesign2342]

Cmp is a fabrication step...

[@satishvasamsetti2399]

@@analoglayoutdesign2342 mechanical part of ic means i didnt get that

[@ANKITSINGH-md9ou]

Sir, at 6:43 ,, why how does, area decreases as capacitance increases,, ??? C is directly proportional to A from the equation.. so it should increase... correct me if I am wrong.

[@analoglayoutdesign2342]

When we decrease the area between the plates of capacitor, the density of capacitor increases...hence we can achieve same capacitance in lesser area..bcos capacitance is inversely proportional to distance between the plates

[@vijanvijan1936]

Mosfet capacitance video sir

[@analoglayoutdesign2342]

Is it not covered?

[@N.AJAYKUMAR]

hello sir, How mom and mim capacitances helps to the layout?

[@analoglayoutdesign2342]

will have a separate video on capacitor matching... this was basic theory of different types of capacitors..next we will look into matching.

[@N.AJAYKUMAR]

@@analoglayoutdesign2342 Thank you