schematic @ 11:06 I think the inverter before the final AND should not be located at the output of the last flop. It should be at the other leg of the AND gate after the double-sync waveform @ 4:21 shows that the pulse = (! sampled ) & ack, so it is the "sampled" signal from double-sync cell gets inverted Other than that, great video! I am watching your other videos on apb protoco and glitch free mux and subscribed. Keep up with the good work!!
Is there a limit to how fast the pulses can be in the clkA domain? Like it the pulses were on every 3rd clkA rising edge, would the pulse detector be able to capture them?
Hi, for the first level mux, there is a PA input. Initially when there is a pulse o/p of first level mux gets set. and it will be cleared only when there is a ack from receiver domain. When 2nd time pulse comes, it will be sampled only if the 1st output has been cleared by ACK, otherwise we will ignore the pulse. Once the Req has been cleared it will be able to take 2nd pulse on the same PA input. There is no need of OR gate. hope this is clear.
@@Electronicspedia for the first level mux, it will be cleared when there is a ack from receiver domain. When 2nd time pulse（PA） comes, it will be sampled, but meaningful only if the 1st output has been cleared by ACK, otherwise we will ignore the pulse. As the previous req pulse is not end.
Great Video. One feedback. Looks like the edge detection circuit is wrong in your schematic. you are showing +ve edge detection circuit instead of -ve edge in your schematic. Thanks
Fifo synchronizers required when we have stream of multibit data to be transferred from one domain to another domain. But with handshake technique we can not transfer multibit and also stream of data.
we can use handahake for multi bit synx also but inly tge thing is we cannot synchronize the stream data with handshake so that was the reason we moves to fido
Hi, CDC technique is applicable to digital signals, where the value of a signal is either '0' or '1'. Whenever there is a metastability the signal either will be logic 0 or 1. In analog signals we have continuous values for which we don't do CDC analysis.
Please Like, Share and Subscribe to my channel ua-cam.com/channels/3mTACG8vPWsHQFMfxzeDZg.html
schematic @ 11:06
I think the inverter before the final AND should not be located at the output of the last flop. It should be at the other leg of the AND gate after the double-sync
waveform @ 4:21 shows that the pulse = (! sampled ) & ack, so it is the "sampled" signal from double-sync cell gets inverted
Other than that, great video! I am watching your other videos on apb protoco and glitch free mux and subscribed. Keep up with the good work!!
Please keep up the good work...
Well explained. Thanks
Is there a limit to how fast the pulses can be in the clkA domain? Like it the pulses were on every 3rd clkA rising edge, would the pulse detector be able to capture them?
for the double synch of the ack signal the clock used is clka?
Great video, can you please explain the example of continuous changing pulse, how to do CDC on that?
Hi Please watch this video, i have explained
ua-cam.com/video/ovQ5VYlEc8o/v-deo.html
thanks bro! that's very clear. Btw, did you post setup time and hold time video?
Hi
@8.21 you used a +ve edge detection, i think it should be neg. Edge detection ckt at output ..
Curious to know why it has to be negative edge detection ckt?
@@Electronicspedia yes exactly
how do you feed new value? understand the reason of having 2 muxs on input side. but I think possible OR gate missing on input of 1st mux. agree?
Hi, for the first level mux, there is a PA input. Initially when there is a pulse o/p of first level mux gets set. and it will be cleared only when there is a ack from receiver domain.
When 2nd time pulse comes, it will be sampled only if the 1st output has been cleared by ACK, otherwise we will ignore the pulse.
Once the Req has been cleared it will be able to take 2nd pulse on the same PA input. There is no need of OR gate.
hope this is clear.
@@Electronicspedia actually its not clear. I don't see path/connection to get new value. all above stuff I understand.
@@Electronicspedia is PA would be your new value?
Yes PA is the new value. Everytime new pulse comes in, will be available on PA
@@Electronicspedia for the first level mux, it will be cleared when there is a ack from receiver domain.
When 2nd time pulse（PA） comes, it will be sampled, but meaningful only if the 1st output has been cleared by ACK, otherwise we will ignore the pulse. As the previous req pulse is not end.
Great Video. One feedback. Looks like the edge detection circuit is wrong in your schematic. you are showing +ve edge detection circuit instead of -ve edge in your schematic. Thanks
It looks correct.
7:58 - Here for the positive edge we detect change as follows
Posedge = din & ~dout
3:45 why sample b would comes down with clk A posedge?
I think it should comes down with clk B posedge
Hi another query
What is the drawback of handshake technique which motivates us to move to FIFO syncronizers?
More clearly saying why we need fifo syncronizers if we have this handshake technique..
Fifo synchronizers required when we have stream of multibit data to be transferred from one domain to another domain. But with handshake technique we can not transfer multibit and also stream of data.
we can use handahake for multi bit synx also but inly tge thing is we cannot synchronize the stream data with handshake so that was the reason we moves to fido
Dear sir, can you provide Verilog code for this and the 2 flop synchronizer? Thanx!
Can you please use a better camera or use it in a different orientation. Video brightness is not consistant.
Thanks for your feedback, will try to take care of it. 👍
Sir, how do we handle analog signals in CDC?
Hi, CDC technique is applicable to digital signals, where the value of a signal is either '0' or '1'. Whenever there is a metastability the signal either will be logic 0 or 1.
In analog signals we have continuous values for which we don't do CDC analysis.