This is the only video I have ever found that discusses metastability and synchronization accurately. There is an incredible amount of garbage published online on this topic. It's a shame this video doesn't go deeper and, in particular, discuss the issue of synchronizing > 1 related bits of data.
The whole point of metastability is that it is probabilistic/random, to know how to fix it is similar to saying an infinite loop can be detected and terminated. The most we can do is wait for it to stabilize to either 0 or 1 so the metastability doesn't cascade throughout the entire circuit, and perhaps include some error detection/correction techniques to minimize the damage.
Thanks for such an awesome explanation. I have a question if you can answer. if there is a timing violation and the output goes to the metastable state but do we get the correct output once it comes out of the metastable state or the output can go to either of the logic high or logic low as can be seen the waveform at 4:57?
Hi, One question on 2 flop synchronizer, the settling of metastability causes latency issue at the recever side, as for a signal changing from 0->1 at flop1 might settle to 1 or 0 before getting sampled by flop2, but will settle to value 1 in next clock So if it is settle in first clock the latency is 2 else the latency will be 3 How to update design to make this latency a fix value Considering both clock same frequency with phase difference
Can't we use a lock up latch instead of a flip flop in the place of a synchronizer ?? Lockup latch with the opposite clock edge connected with the first clock domain does the same job right ?? So, in synchronizers why are we using a flop ? Please explain...
I have a question, Im using clock gating in my design. My question is: the clock gating should affect the dual flop synchronizer or the synchronizer must have the free clock always?
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Why UA-cam doesn't recommend such videos at the top! Very well explained!
This is the only video I have ever found that discusses metastability and synchronization accurately. There is an incredible amount of garbage published online on this topic. It's a shame this video doesn't go deeper and, in particular, discuss the issue of synchronizing > 1 related bits of data.
Perfect! I will watch the whole series now..
the best video for synchronizer!!
شكرا جزاك الله خيرا Thanks
Although a synchroniser avoids metastability, it can corrupt the data by settling it into incorrect state. How do we correct it?
The whole point of metastability is that it is probabilistic/random, to know how to fix it is similar to saying an infinite loop can be detected and terminated. The most we can do is wait for it to stabilize to either 0 or 1 so the metastability doesn't cascade throughout the entire circuit, and perhaps include some error detection/correction techniques to minimize the damage.
Thank you for your awesome explanation!
Very good video, surprised this doesn't have more views
Thanks for such an awesome explanation.
I have a question if you can answer. if there is a timing violation and the output goes to the metastable state but do we get the correct output once it comes out of the metastable state or the output can go to either of the logic high or logic low as can be seen the waveform at 4:57?
You cannot tell the output of the system after the metastability ends, and you cannot tell for how long it will be in metastable condition.
Excellent video, thanks!
Hi,
One question on 2 flop synchronizer, the settling of metastability causes latency issue at the recever side, as for a signal changing from 0->1 at flop1 might settle to 1 or 0 before getting sampled by flop2, but will settle to value 1 in next clock
So if it is settle in first clock the latency is 2 else the latency will be 3
How to update design to make this latency a fix value
Considering both clock same frequency with phase difference
Can't we use a lock up latch instead of a flip flop in the place of a synchronizer ?? Lockup latch with the opposite clock edge connected with the first clock domain does the same job right ?? So, in synchronizers why are we using a flop ? Please explain...
excellent
I have a question,
Im using clock gating in my design. My question is: the clock gating should affect the dual flop synchronizer or the synchronizer must have the free clock always?
Very good explaination, should not be this low view count. Anyway great job
Wow! salute
Ty sir