because initially that capacitor is fully charged as vout is vdd and vin is 0v, and at the instance our vin goes to vdd , the capacitor is still has charge so it increase the vout to some extent resulting in the spike .
Since high frequency operation, change in input is reflected on capacitor plates from Vin = 0 till Vin = Vtn which gives the bump. For Vin>Vtn , NMOS becomes ON and discharges the capacitor. The theory that Gate to Drain Capacitance doesn't allow sudden change at output - how does it fit?
@@socialogic9777 the thing is capacitor should store charge to vdd, so at the instance when vin goes high, to maintain store charge upto vdd , it increases the vd to few seconds, due to which we observe the spike , the same concept is for negative spike also.
Nice addition of the questions being asked in the class, clears our doubts too to some extent.
Why cgd make instant rise in voltage value at beginning???
Why it is not falling???
because initially that capacitor is fully charged as vout is vdd and vin is 0v, and at the instance our vin goes to vdd , the capacitor is still has charge so it increase the vout to some extent resulting in the spike .
But load capacitance voltage cannot go above VDD. As it is being charged by VDD.
Since high frequency operation, change in input is reflected on capacitor plates from Vin = 0 till Vin = Vtn which gives the bump. For Vin>Vtn , NMOS becomes ON and discharges the capacitor.
The theory that Gate to Drain Capacitance doesn't allow sudden change at output - how does it fit?
@@socialogic9777 the thing is capacitor should store charge to vdd, so at the instance when vin goes high, to maintain store charge upto vdd , it increases the vd to few seconds, due to which we observe the spike , the same concept is for negative spike also.