Here 2nd step s=0,r=1, (1+Q')' in that assumption we have to consider 1+A=1, so in above we have 1'+Q =1' which is nothing but 0,and 2nd condition - (1+Q)'=0.Q'=0
I can understand your classes easily. Very good explanation. First of all i salute you madam. I need softcopy of your classes. How can i retrieve madam.
Rather than doing the complex calculation in the above video, we can do S=1 Qn+1 =1 and R=1 Qn+1 =0 For S=0 R=0 Qn and for S=1 R=1 indeterminant but above video is good and awesome I really enjoyed lecture.........
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ma'am i cannot express my gratitude towards you. thank u so much!!!
Thanks ma'am 🙏🏻for providing amazing video's.They are really helpful.
Very informative and helpful also easy understanding lectures...
God bless you ma'am
Absolutely best teacher in you tube
Very useful, explanation can be understandable by anyone.... great work.
great awesome explanation........very very helpful....hats off..........................
THANKS MADAM.IT'S REALLY HELP US TO UNDERSTAND MORE BETTER AND EASY.
Very useful and u r explanation is too good I have been watching u r since 2 months it is useful for our coure
I thank ful to you mam.
I am always confused this topic.
Really thanks
All r best vdeos for explanation
Here 2nd step s=0,r=1, (1+Q')' in that assumption we have to consider 1+A=1, so in above we have 1'+Q =1' which is nothing but 0,and 2nd condition - (1+Q)'=0.Q'=0
This helped my stupid friend understand the concept, thanks.
The way you explained is better which makes us easy to understand
really your way of explaining is very easy to understanding. thank you for making videos mam
Veeeeery useful information. Thanks a lot for doing your videos in English 🤗
all your classes are very nice and great explanations.
i'm expecting the class about Edge Triggered flip flop.
I was alsoo
Very useful, explanation can be understandable by anyone....
Very nice explanation. Got full clarity. Thankyou
Today is my exam you are helping me a lot thank you so much Mam don't stop you teaching mam continue🤗 once again thank you mam🤝
Ambiguity between Logic circuit and Logic symbol. please make update
WAY BETTER THAN MY COLLEGE
Tq so much sis, I can't tell my happiness in words
Absolutely perfect... You should be proud ma'am, you are doing an amazing job👍👍
Thank you so much maam your teaching skills are awesome
It's very helpful for our sem exam madam
Thank you so much mam
This video is very helpful for me......
Tq mam.the way of explanation is nice and very helpful 🙏
thank you maam....... just loved the way of your lecture
great series thank you very much
Multi tallented maam ...sab kuch pada sakhti hai..
Thanks mam for your knowledge sharing
I can understand your classes easily. Very good explanation. First of all i salute you madam. I need softcopy of your classes. How can i retrieve madam.
Nice Madam. I think everyone understand better
In 2nd step also if we consider complement part then we get qn bar not 0 in complement part but why should we consider only in 3 rd step
Soo nice well explained👌👌👌👌👌👌👌👌👌👌👌👌👌👌👌👌👌👌
Very awesome lecture mam thank you so much
thanks madam
great lecture cleared my all doubts
Very help full for me
great madam thank you very much nice explained
Very very helping ..
Abbaa sai ram 🙏🏻🙏🏻 ... tq madam 💖
very nice lecture
In the second condition calculate Qn+1 bar
Bro did you got the answer
Thank you Ma'am 💐
i love u mam you are
a life saver
A very good video mam... But can u plz tell me how can we get MEMORY state of this latch
Superb mam 👌
thanks for your video lecture
NYC lectures.....👍👌
can anyone tell name of this mam,don't no how to thank u ,iam always used to see ur video they are so easy to understand ,thank u so much mam
Excellent explanation mam
excellent class
Excellent mqm
Mam too good👌👌👌
Thank you madam
Mam you are awesome
💐
Excellent madam I fully understand
😍 thank you so much
is nor and nand equation is same in sr flip flop pls explain nor gate equation
Thankyou mam for upload such type of vedio lecture
👌👌👌👌👌👌 explanation
In the previous video, you said that Latches are Synchronous.
Muito obrigado, sua explicação me ajudou muito.
Oho! I didn't expect to spot a Portuguese here 😄
ronaldo goat
THANK YOU MADAM VERY HELPFUL VIDEO REALLY,,,,THANK U
Rather than doing the complex calculation in the above video, we can do S=1 Qn+1 =1 and R=1 Qn+1 =0 For S=0 R=0 Qn and for S=1 R=1 indeterminant but above video is good and awesome I really enjoyed lecture.........
Thank you so much mam
Ur teaching is mind-blowing mam please teach network analysis subject also mam please send soon mam
why it is called active high St latch. Kindly explain mam
Bcoz, nor gate works for 0, 0 inputs the output is 1.. SR high latch means, from 0 state to 1 high state, so it is called Sr high state.
Thank you ✌️
@tutorialspoint please explain about state diagram
best explaination
nice explanation
Thank you ma'am.
Thanku madam .u have clear all my dout
great work any one can understand it
Intresting
very helpful vdo....!
Jabardast mam
In 3rd step why should you consider only complement part normal qn+1 also has qn
Hello Mam,
Is it that while using NAND gate in latches and flip flops we can have R & S anywhere as either normal path or complementary path?
Yes
At the end , while writing the short version of the truth table why did you take Qn values to be don't care values????
Very good
Thank you madam...
Lajawab
Mam, why segregation is done in truth table
Because if sagrigation done then only we observe change in qn.s and r same
Ma' am g tose tay tabahi pa dette eho g ma' am samjawy tay kano samajh na away ge
What project can you recommend for me as a telecommunication student
Measuring speed of wind to design a warning system also that predicts tunnel fire
Mam from where msc electronics is best
Apke video ka playlist Kya hai channel me
Thanks much
isn't it is Present input and past output right?
could anyone please explain why r is taken as first input instead of s?
play the video again and you will hear when she explained the reason. it is this way when using NOR gates and reverse when using NAND gates.
@@cfv717 bro in 2nd condition y she didn't take 0+Qn bar which is equal to 1
well explained.Thank you
Latch is asynchronous bz no clock pulse used
I not understand case 3 why it is 1 madam please madam help me
i think its a mistake
In nor gate u can add anything with 1 the answer is 0 . So the second case answer is wrong
Plz explains the logic symbol
Your analogy of: 1 + anything = 0 is wrong
(Assume the case R=0, S=1)
actually the process is: (0+Qn)' = 1.Qn' = Qn
similarly: (1+Qn)' = 0.Qn' = 0
Yes
Super mam