Thanks for the video. Can i ask you sir a question? Can the drain of M2 be connected to the gate instead of M1? It seems the calculation is still the same though.
I hav done simulation of CTAT & PTAT Ckts in 40nm , but the same circuits simulation I have tried in 16nm with using pnp_mac in cadence tool, but without any circuit change it always showing fatal error.
we need two conditions to met (as i explained in video) 1. equal current through the branches and same voltage at the source node of nmos (vd and v2 should be equal). nmos current mirror will ensure the second condition also
Hafeez KT hello, thanks for the reply. if we measure from top, we have a voltage of VDD-VGS on both the legs.So, we can maintain the same voltage just by using pmos. So, why do we need to use nmos.
Ananthesh K V Hi, For easy to understand, I think that idea is to reduce the chanel length modulation affect. I_copy/I_ref ~ (W/L ratio)*(1+lamda*Vds1)/(1+lamda*Vds2), if we want to have the exactly copied current and neglect the chanel length modulation effect, we need to make sure Vds1 = Vds2
Hello sir, How we can take that pnp transistor in virtuoso.?? I'm not finding the same transistor and if I used another pnp which is there it's showing an error....
Hi Sir, If we make the left PMOS as diode connected instead of the right PMOS, will there be any issue?
following
Thanks for the video.
Can i ask you sir a question?
Can the drain of M2 be connected to the gate instead of M1?
It seems the calculation is still the same though.
Thanks for the Vref,
Can you help me how to get Iref (current reference) of 240uA out of the Vref
I hav done simulation of CTAT & PTAT Ckts in 40nm , but the same circuits simulation I have tried in 16nm with using pnp_mac in cadence tool, but without any circuit change it always showing fatal error.
Hey,
In the PTAT you explained, only the PMOS current mirror is enough right? Why did you add NMOS stacked below to the PMOS mirror?
we need two conditions to met (as i explained in video) 1. equal current through the branches and same voltage at the source node of nmos (vd and v2 should be equal). nmos current mirror will ensure the second condition also
Hafeez KT
hello,
thanks for the reply.
if we measure from top, we have a voltage of VDD-VGS on both the legs.So, we can maintain the same voltage just by using pmos. So, why do we need to use nmos.
no. vdd-vgs on one branch and vdd-vds on the other branch. they need not to be equal
Ananthesh K V Hi, For easy to understand, I think that idea is to reduce the chanel length modulation affect. I_copy/I_ref ~ (W/L ratio)*(1+lamda*Vds1)/(1+lamda*Vds2), if we want to have the exactly copied current and neglect the chanel length modulation effect, we need to make sure Vds1 = Vds2
@@hafeezkt... Thanks a ton for nice videos and also for above clarification.
Hello sir, How we can take that pnp transistor in virtuoso.??
I'm not finding the same transistor and if I used another pnp which is there it's showing an error....
same here
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