@@InderjitSingh87 sir can you plz make a vedeo on wilson current mirror and super wilson current mirror simulation . How exactle we have to balance it like w/l ratio, vgs matching etc.
Hi sir,you arrived at the correct result but your train of thought is incorrect. Why Vgd3=0? and whats with this Vp+Vth and Vq-Vth? The correct way of thinking is Min voltage at X is VGST1 +VT1. The extra VGST is for it to drive current Iref through M1, similarly at point Q, min of VQ is VGST0+VT0 +VXmin=VGST0+VT0+VGST1+VT1 Now due to current mirror action by M3-M0,M2 is ensured to be in saturation as Vy follows Vx,hence in saturation.(only if Vp>VT+VGST) So now for M3 to be in saturation VPmin=VQmin-VT3 so if all VT are same,we can rewrite the equation as VPmin=VGST0+VGST1+VT you can sort of plot it as Iout vs Vout and see post Vpmin the Iout flattens out.
Its point j, yes both sides have Vth added deliberately to balance, then VQ -Vth is equal to Vp +Vth, in reality this Vp + Vth is conventionally Vp voltage which is equal to VQ + Vth, so that why Vth is added to Vp.
In case of MOSFET M1, its Gate and Drain terminal are tied together, and Source terminal is grounded, Assuming body is also connected to source, now VGS1 = VDS1, and VX is measured between Drain and ground i.e VDS1 itself, thats why VX = VDS1 = VGS1
What an explaination .... Best video for Analog design
Really helpful video sir would be really helpful if you could provide the onenote links too or the pdfs of the lectures
amazing explanation.
Glad you think so!
beautiful explanation sir . i was having so much confusion in modified Wilson current mirror, that u just resolved in blink of 30 mins
Glad to hear that
Very helpful. Thanks a lot.
You're welcome!
Superb efforts and great content . Atleast you are helping vlsi student a lot . Thank you sir plz keep uploading .
Thank you, I will
@@InderjitSingh87 sir can you plz make a vedeo on wilson current mirror and super wilson current mirror simulation . How exactle we have to balance it like w/l ratio, vgs matching etc.
@@renukaatri1206 Sure, I am occupied currently with work, will upload soon.
Hi sir,you arrived at the correct result but your train of thought is incorrect. Why Vgd3=0? and whats with this Vp+Vth and Vq-Vth?
The correct way of thinking is
Min voltage at X is VGST1 +VT1. The extra VGST is for it to drive current Iref through M1, similarly at point Q, min of VQ is
VGST0+VT0 +VXmin=VGST0+VT0+VGST1+VT1
Now due to current mirror action by M3-M0,M2 is ensured to be in saturation as Vy follows Vx,hence in saturation.(only if Vp>VT+VGST)
So now for M3 to be in saturation
VPmin=VQmin-VT3
so if all VT are same,we can rewrite the equation as
VPmin=VGST0+VGST1+VT
you can sort of plot it as Iout vs Vout and see post Vpmin the Iout flattens out.
Thank you!!!
This was explained very well while explaining assumed idealogies other videos don't mention!!
thank you, glad it is helpful.
29:30 Why "Vgd3" needs to be zero for M3 to be in saturation?
Clean and neat explanation sir. Thank you sir
Where can I find these handouts ?
thanks Harish, handouts aren't available currently. You can take notes from videos itself.
Sir, In the minimum allowable voltage at Node P calculation section, for M3 to be in saturation, how did we arrive that VGD3 should be 0?
VGD3 = VGS - VDS = 0 means, VGS is always greater than VDS, meaning M3 is in saturation
@@InderjitSingh87why you didn't use Vds>Vgs-Vth so Vd>Vg-Vth so Vgd
Where can I get ur written notes ??
Sir,
Here Vp is only 2 overdrive , R.H. and L.H.S both have Vth term.Kindly check.
Its point j, yes both sides have Vth added deliberately to balance, then VQ -Vth is equal to Vp +Vth, in reality this Vp + Vth is conventionally Vp voltage which is equal to VQ + Vth, so that why Vth is added to Vp.
Sir plz take the current mirror circuit in Electric Vlsi tool and simulation in LTSpice , I find it very difficult to get a proper simulation result
yes sure, will try
Sir can u provide pdf of AVLSI course
Notes are not available. I always encourage learners to note down important concepts from the video. That will be your notes.
Sir
why vgd3 =0?
VGD3 = VGS - VDS = 0 means, VGS is always greater than VDS, meaning M3 is in saturation
Can you please send the written notes please 🙏🙏🙏 please
Notes are not available. I always encourage learners to note down important concepts from the video. That will be your notes.
How VX= VDS1
In case of MOSFET M1, its Gate and Drain terminal are tied together, and Source terminal is grounded, Assuming body is also connected to source, now VGS1 = VDS1, and VX is measured between Drain and ground i.e VDS1 itself, thats why VX = VDS1 = VGS1
Can you please send the written notes please 🙏🙏🙏 please
Notes are not available. I always encourage learners to note down important concepts from the video. That will be your notes.