Introduction to VHDL - Part 1: Behavioral Modeling

[@victormbebe3797]

REAL COOL

[@xxmemestar69xx82]

Doesn’t this example demonstrate the structural model?

[@diabianeyah]

The logic gates alone as implemented in the video are behavioural because we are not describing the “wiring” between components.

[@praneethnekkanti5199]

this is dataflow model behaviour modeling

[@JOFFERSONGATUS]

how could i do the data flow model? thanks for the answer

[@diabianeyah]

I'm not sure this is what you mean but try open your project in Quartus then go to:
Tools -> Netlist viewers -> RTL viewer (or State Machine viewer).

[@kravenkrave]

@@diabianeyah I've been used Xilinx ISE and then some of our activities is so hard like adders and subtractors, comparator and multiplexer and demultiplexer. we hope you can teach us before end of sem. thank you. keep up

[@diabianeyah]

@@kravenkrave I have a video about implementing an adder and a multiplexer in VHDL in my channel.