Modeling Style in VHDL || VLSI Unit1 ch. 3

[@Akankshamishra-t9l]

bhai i like your voice
and it was a very good explanation.

[@mayank_2199]

Yaar VHDL ki or videos kaha se milegi i mean any other channel's

[@kabandajamir9844]

So nice thanks

[@DownJeans641]

bhai zyada conditions likhni hain toh comma lagayenge?
For example:
if a = '0', b = '0', c = '0' then
y = '0';

[@rihanturk2305]

Thanks sir ❤

[@shameenasayed8004]

Thank you ❣️

[@Shahbaz_S_Shaikh4]

Hii bhai kuch problem huee kya iske baad aapne video nhi banayiiii aap bht acche se padhate ho👍👍😍😍❤❤❤

[@anujsingh116]

Is structural coding n structural modeling same

[@Ashryzen]

Then what is the difference between data flow and behaviour code

[@VALUE_FOR_MONEY_VFM]

GooD❤

[@PKJ11]

Warning : the structural code is not correct it doesn't have port mapping,component declaration or any logic.

[@himanshuranjanshrivastav7407]

Please upload lecture on all units 🙏

[@ronak_maira_28]

thanku

[@nikhiltyagi412]

Level of modelling yeah hi h na

[@educationarena6308]

Haan

[@himanshuranjanshrivastav7407]

Vlsi design exam on 19th

[@niteshnitx]

Exam is on 22nd April 🥲

[@anujsingh116]

23 April 🤧

[@niteshnitx]

@@anujsingh116 All the best bro 🥺

[@anujsingh116]

@@niteshnitxthanks and same to u 🥲

[@niteshnitx]

@@anujsingh116 Thanks bro 😊❤️

[@JethaaJiii]

Bhai aaj dekh rha hu... Aaj hi exam hai 2 baje se... Abhi 12 baj rha h

[@LouieRod-w7n]

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