Hello Sir. Thank you very much for this very clear description on SRAM Design. However, I tried implementing the demo exactly in LTSpice but the values of Bit and Bit_bar are very noisy. Do I have to adjust the width of the NMOS and PMOS transistors (Weak, Med, Strong) for proper current flow? If so, what are the best values to use considering the transistors are from the tsmc018.lib? Thank you very much again.
Yes, the transistors arte required to be sized propoerly. You may mail be the .asc file if the problem is not resolved. sanjay.vidhyadharan@pilani.bits-pilani.ac.in
I have kept lenght as 180 nm for all mosfets. The minmum width is 400 n. I have explained the sizing constraints. You vany try and let me know in case of any issues.
Sir, I am getting Waveform for Q and Write functions as steps with spikes, am not getting Pulse output can you specify the transistors sizes and i have mailed the .asc file
Static Power for inveter with input low would be Vdd * I off of NMOS. Like wise Static Power for inveter with input high would be Vdd * I off of PMOS. Power of invete would be 1/2 *Vdd square* freq*C_load
I would prefer students to try it out once themselves. In case you are not getting the desired output you can mail me the .asc file , I will have a look and let you know the issues. sanjay.vidhyadharan@pilani.bits-pilani.ac.in
Dear Professor, please, could you help me to calculate SNM for read and write operation. How I can plot VTC curces of the two both inverters in SRAM 6T . Thank you for your help. Best wishes
Sir, I mailed you the asc file. I am getting problem in plot of Q while observing for data write operation , maybe it's because of proper sizing, i tried so many times, kindly look into it.
Sir, I was a little confused when you said Write logic gate. What type of logic gate would it be?
Sir, I am getting Waveform for Q and Write functions as steps with spikes, am not getting Pulse output
can you specify the transistors sizes
Could you plase mail me the .asc file I wwill have a look and revert back to you.
sanjay.vidhyadharan@pilani.bits-pilani.ac.in
@@SanjayVidhyadharan sir i am also facing the same problem in it
how can i calculate leakage current distribution through different cmos transistors in both states high and low
sanjayvidhyadharan.in/courses/vlsi-design-using-lt-spice/
Hello Sir. Thank you very much for this very clear description on SRAM Design. However, I tried implementing the demo exactly in LTSpice but the values of Bit and Bit_bar are very noisy. Do I have to adjust the width of the NMOS and PMOS transistors (Weak, Med, Strong) for proper current flow? If so, what are the best values to use considering the transistors are from the tsmc018.lib? Thank you very much again.
Yes, the transistors arte required to be sized propoerly. You may mail be the .asc file if the problem is not resolved. sanjay.vidhyadharan@pilani.bits-pilani.ac.in
Hello sir. Please make a video of calculation of static power, dynamic power and delay of ripple carry adder sir
have a loo at lecture 1 for power and delay measuremnts in LT spice.
sanjayvidhyadharan.in/courses/vlsi-design-using-lt-spice/
hii sir, what should be length and width of nmos and pmos transistors?
I have kept lenght as 180 nm for all mosfets. The minmum width is 400 n. I have explained the sizing constraints. You vany try and let me know in case of any issues.
Sir, I am getting Waveform for Q and Write functions as steps with spikes, am not getting Pulse output
can you specify the transistors sizes and i have mailed the .asc file
You may mailme the asc file. I shall have a lok and revert back to you
Kindly, what are the equations used to calculate static and dynamic power for multi state cmos inverters?
Static Power for inveter with input low would be Vdd * I off of NMOS. Like wise Static Power for inveter with input high would be Vdd * I off of PMOS. Power of invete would be 1/2 *Vdd square* freq*C_load
Sir can we do same in FINFET technology and u said this is 6t sram but here used 8 to 10t so i am confused about it could you please explain me sir
The basic cell is 6T. follw this sanjayvidhyadharan.in/courses/digital-vlsi/. i have exaplned how to import lower technolgy files.
Hello Sir, i have done it using T-spice but i can't properly write the data into the SRAM cell, can you please help
You may mail me the .asc file. You might not have sized the transistors correctly .
sanjayv@hyderabad.bits-pilani.ac.in
@@SanjayVidhyadharan Sir i am doing it using a NETLIST on Tanner-Spice, so i have the .sp file, should i send it to you.?
sir , will the sense amplifier work for DRAM?
It should
Sir, I am getting Waveform for Q and Write functions as steps with spikes, am not getting Pulse output
You can mail me the .asc file. I shall have a look
can you please provide one video for the ideal mode?
When i get some free time I shall try
Sir can you Please send me making video of sram circuit.
Thank you sir for the video. How can we measure SNM for the circuit
You can do a plot of Qbar by sweeping Q. Export data to excel and draw SNM plot. In Cadence you can plot Q Vs Qbar and Qbar vs Q directly,
Will it be used for a dram cell aswell...??
You may plesea refer to lecture 11 for DRAM operation from the link given below
sanjayvidhyadharan.in/courses/advanced-vlsi/
Sir, Can u mention the width & length of all transistors in the design?
Cz I'm getting little different waveform of Q.
I would prefer students to try it out once themselves. In case you are not getting the desired output you can mail me the .asc file , I will have a look and let you know the issues.
sanjay.vidhyadharan@pilani.bits-pilani.ac.in
Did u get output?
Sir tell me the each transistor sizing for SRAM
Try wil minimum permissible parameters . Mail me the asc file in case you are not getting the desired results
Dear Professor, please, could you help me to calculate SNM for read and write operation. How I can plot VTC curces of the two both inverters in SRAM 6T .
Thank you for your help.
Best wishes
In LT SPICE you can export the data of single inveter into an exce sheet and there after plot the SNM in excel
@@SanjayVidhyadharan Thank you professor, please, I have send you a email to correct me my SRAM project. Thank you for your helps. Best wishes.
Sir, I mailed you the asc file. I am getting problem in plot of Q while observing for data write operation , maybe it's because of proper sizing, i tried so many times, kindly look into it.
Let me check
@@SanjayVidhyadharan Professor, Same problem for me also. While writing i am unable to write Q properly. Can you help me?
I have also Mailed my ASC file to you professor. Kindly Review and reply ASAP!
Sir even i have mail please help me out
sir what sizing you have used
You can use minimum sizes for all transistors except for the pass transistors which require to be scaled up a little.
@@SanjayVidhyadharan Sir,still i am not getting the proper output for q
Sir, can you share the same for 9T and 12T sram cells
You can try it out and in case of any problemmail me at sanjay.vidhyadharan@pilani.bits-pilani.ac.in
@@SanjayVidhyadharan sir i am trying simulation of 12 T but i am not sure about the voltage source placements and drivers
hi sir , could you please share those files to us
sir can i get asc file for this please
Rahman, Try it yourself. If you are not getting the desired results mail me the .asc mail, i will let you know where you are going wrong
Sir LT spice is open source
You can download LT SPICE for free from their webpage
Sir
What is the querry?
@@SanjayVidhyadharan sir do you know how to work in reliability (Relxpert)in. Cadence
@@SanjayVidhyadharan sir
sir could you please give your mail id so that I can send my .asc file . it is not working
anjay.vidhyadharan@pilani.bits-pilani.ac.in