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Your videos are very good, sir! A lot of respect for your work!

How to solve it with sr flip flop

Sir, I was a little confused when you said Write logic gate. What type of logic gate would it be?

Hi sir, in LTSPICE we fix the terminals based on biasing or is it fixed by the software?

hi sir , could you please share those files to us

Note 5:42 floating node... Why we need another transistor

i download version 24.0.12, and i dont see icon .op in tabbar, what should i do now?

Excellent explanation.

hii sir, what should be length and width of nmos and pmos transistors?

Can you please tell me what is the value of w/L ratio of nmos and remaining pmos which is present in inverter

Sir y is taken for voltage across capacitor but solution is written for i why sir

Hlo sir, I have done the same proces what u have explained but it is showing that"could not open include file tsmc018.lib"

useless

Sir can you please tell me where i can find the 7nm finfet file ,because the sight is not working

Sir, could you please explain why mirror images of Nmos circuit is taken as PMos circuit, could you please touch a bit on that? (I get it that the mirrored alternative can reduce the gate sizes in carry's case, and also it works only for the circuits in which inverting individual inputs is gives the same effect as inverting the whole function output, but why this logic for mirroring??)

thanks

Thank you for the lecture. It's been so helpful. I have one question. In page 13, while talking about untestable path delay, why is ↓P2 untestable? I suppose ↓P2 should be a validatable robust test(VRN) as ↑P2 is a VRN due to ↓P3 being a robust test. Please correct me if I'm wrong.

LTSPICE does not support FinFET device simulation 🙃

Sir can you do a vedio on how to import GNRFET MODEL into cadence sir

why do we have to convert vanangle 10 to angle 30? pls tell

There is a error in qs 2 ,

Very much knowledge in this video , thanks for it

ay too many ads in one video

Send a code sir

Sir in the bridging fault question (A-B) for the wired-AND there is no fault for the Test Vector 0 1 1 as it gives output as 1. but u gave there as zero (0) ,its slightly confusing me sir.

Sir, I am getting Waveform for Q and Write functions as steps with spikes, am not getting Pulse output can you specify the transistors sizes and i have mailed the .asc file

today is my exam, still watching your lecture thank you so much

Sir can we do same in FINFET technology and u said this is 6t sram but here used 8 to 10t so i am confused about it could you please explain me sir

55:27 'Guru Brahma, Guru Vishnu, Guru Devo Maheshwara, Guru Sakshat Parabrahma, Tasmai Shri Guruve Namah.'Your teaching is invaluable and goes far beyond any monetary value

I'm a student of GRIET, hyd. I found your UA-cam channel searching for finFETs for my major project, coincidently I am also preparing for VEDA IIT entrance exam. Your lectures are helping me a lot. Thankyou sir

Sir how can I get these ppts...

able to understand everything

may know what emulator you are using

Thx sir😂

Awesome lecture

thankyou sir for great explanation, I am not getting why we are looking hold time for the same clock edge....i watched the part multiple times, still not getting

Could you please explain how CRP is 1.4ns at 1:04:24

Very Nice Sir

Excellent lecture on the fundamentals, with the right amount of detail for an electronic engineer,

Very helpful sir, thank you

One of the best videos seen so far

whos that dumb person asking illogical question

Thanks , able to setup 180nm using this tutorial. You just need to create tsmc018.sp ( instead of tsmc018.lib for LTSpice ) in the model file and rest of the steps remain same.

great explanation! very helpful

Detailed explanation for understanding purpose awesome sir📈

woah! thanks a lot!

Excellent explanation sir, Is we use this 180nm pdk file for ADS 2021 software and we can able to to use BSIM 4.

"Could you please share the LTspice code for the VCO circuit mentioned above?"

Sir tell me the each transistor sizing for SRAM

To calculate Tclk(min) we need to do so by Tclk(min) = tcq+ tlogic+ tsu and if we consider the skew , we subtract del(skew) from the equation. So the Tclk(min) = (6+4+3+3-3-3) = 10n. Hence fmax = 1/10n = 100Mhz. I understand that you directly subtract the slack from Time Period, but iam not able to get that by the general Tclk(min) logic.