Відео

Most welcome

I have explained the sizing constraints in the video, you can try and let me know if you have any issues.

@SanjayVidhyadharan Sir can you make videos about 10 transistors and 9,8,6 transistors sir it's important for us sir pleaee

Ok

I have explained the sizing constraints in the video, you can try and let me know if you have any issues.

Most welcome

Thankyou

add flip flop inputs, according to output fill with SR values thats all.

Rightly saiod by @ragaen3698, Reaplce KJ with SR but values of SR in the table sgould be decideed based on next state

I nay have reffred to the transistor thet needs to be switched on to write the data

we fix the terminals based on circuit configeration

All lenghts are min lenght for technology . I have exepeliend the sizing requiremnets (widhts). Try try once. Reach out to me in case of any issues

For all possible four input combinations. Out put should either be connected to ground or VDD

​@@SanjayVidhyadharan I just added my note point sir. Understood the concept

I still have the older verion on ny desktop. I feel theold one is better. But I am sure all features will be there i the new version too

Thanks. Glad you found it useful.

I have kept lenght as 180 nm for all mosfets. The minmum width is 400 n. I have explained the sizing constraints. You vany try and let me know in case of any issues.

I have kept lenght as 180 nm for all mosfets. The minmum width is 400 n. I have explained the sizing constraints. You vany try and let me know in case of any issues.

Which problem, Can you let ne know the play time

Please make sure that the .lib file is in the same directory as your .asc file, otherwise, you will need to specify the file path in your .asc file.

PTM is now avalible at many web sites for eaxmple mec.umn.edu/ptm

The mirror topology helps in in avery compact layout

My pleasure.

The proceddure may be similar. I have not tried it

The proceddure may be similar. I have not tried it

If you let me know the time of video I can have a look

Posiible. You may post the details

You are welcome. Glad you found it useful.

I shall look into ot

Partail Code might beteher in sanjayvidhyadharan.in/courses/microprocessors-and-interfaces-lab/

Yes you are correct out put would be 1. There is a si mple in slide. Thankyou

You may mailme the asc file. I shall have a lok and revert back to you

All the best

The basic cell is 6T. follw this sanjayvidhyadharan.in/courses/digital-vlsi/. i have exaplned how to import lower technolgy files.

Thanks a lot from the bootom of my haert for the kinf words. May God bless you with lots of happiness and success in life

Best of luck!. You may visit sanjayvidhyadharan.in/all-courses/ there are many cousrses avaliable for free

vist sanjayvidhyadharan.in/all-courses/ . You can download all pdfs. No need to regsister. It is free

Thankyou

EMU 8086 emu.

My pleasure

Thanks for liking

The data need to be stable for a certain amount of time after the clock arrives. The data from previuos clock has aledat settled tocater for set up time. For the hold the data from presnt clock should come slow enough to cater for hold time

@@SanjayVidhyadharan ohh,so the data should come slow,in order to avoid collision

Hold failure means that the data intended to be sampled in the current clock cycle has been overwritten by new data sneaking through to the flip flop due to very fast data path. Ideally the flip flop should have been cutoff before the new data sneaked to its input. Failure to do that leads to hold violation. That is why hold checks are done at the same clock edge since it is a failure of the same clock. Hold failures irrecoverably corrupt data since there is no way the overwritten data can be recovered.

In the bottom path it is 0.8 X3 = 2.4 and top path is 1+1 = 2ns. Only one path will be active in agice\ven circumstsnce hence CPR = 2.4-1= 1.4 ns

Thanks and welcome

Thanks a lot

Most welcome

Thanks a lot