Implementing a combinational logic circuit in VHDL using Quartus Prime Lite

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  • Опубліковано 29 жов 2024

КОМЕНТАРІ • 10

  • @gregben
    @gregben 3 роки тому +1

    Thanks for creating this tutorial. The logic you create with VHDL and place in the FPGA is not "simulated". It is real logic. I should know, I've been working with digital logic since 1975.

  • @Sonic2ist
    @Sonic2ist Рік тому

    very helpful step by step tutorial. thank you very much.

  • @farnazzinnah8541
    @farnazzinnah8541 2 роки тому +1

    It's worth to subscribe to his channel. He helped me finishing my project in one go. Thank you!!!!

  • @warleyxavier7142
    @warleyxavier7142 3 роки тому +1

    Thanks for your tutorial!

  • @김서진-n3y
    @김서진-n3y 2 роки тому

    Thanks for the tutorial:)

  • @namugwanyamarypatience7039
    @namugwanyamarypatience7039 2 роки тому

    Thanks for the very helpful video. What can one do, incase the simulation runs for longer than the set time? What could be the cause of that? I have followed your steps but my simulation runs for more than 10 ns.

  • @mayankpatel7973
    @mayankpatel7973 2 роки тому +1

    I followed the same step as u but my compilation and analysis both are unsuccessful , in analysis it is stating that top level design entity is undefined
    kindly plz guide me as I have to submit some codes and simulation

  • @PengJin-i8k
    @PengJin-i8k 4 роки тому

    thank for ur help

  • @idasol2966
    @idasol2966 3 роки тому +1

    HI It is very good. The best one, but You did not show us how to write the code, You just copied it. Thanks