Hi Victor, Thank you for a fantastic introductory video. I have a question: How does changing the T flipflops to trigger on the negative clock edge cause the counter to count upwards? I thought negative edge vs positive edge wouldn't matter because in the end, it just acts as a trigger to flip the value of the input q. I think something else is happening here.
You're right - something else is happening here. If this circuit were synchronous, then changing the clock edge would just change the clock edge on which the counter outputs changed. It would not change the direction the counter counted in. But this circuit is not synchronous: a ripple counter is not a synchronous design. For a design to be completely synchronous, all the flip-flops must be clocked all the time from the same edge of the same clock. This is not the case here: each flip-flop is clocked by a different clock - the output of the previous flip-flop. Matthew not Victor Victor made the video and created EDA Playground. My company - Doulos - acquired EDA Playground last year and now operates it and maintains it.
i believe it is correct that on negative edge of reset, the counter will work as an UP counter. This is what happens when you build a ripple counter using JK FF as well. for reset = 0(negedge) --> UP counter, for reset = 1(posedge)--> DOWN counter
Hi. Great video! i wanted to know if theres a differnece in [3:0] and [0:3] in defining a variable in verilog. both essentialy define a 4 bit variable.
[3:0] and [0:3] both declare a 4 bit variable in verilog, as you say. The only difference you would encounter is if you tried to access a subset of the bits, for example individual bits. Then with a variable declared [3:0] the left-hand bit or most significant bit (MSB) is [3], whereas with a variable declared [0:3] the left-hand bit or MSB is [0]. Matthew
HI thanks for videos, I am doing FIFO using edaplayground , and would like to see internal signals in waveforms , could you please let me know how to see those
Make sure you have ticked the box "OPen EPWave after run". If you're using VHDL, that's all you need to do. If you're using Verilog/SV, you need to add "$dumpfile("dump.vcd"); $dumpvars(1);" to an initial block in your testbench. Then, after you run the simulation, the waveform viewer opens and you can add signals by clicking on "Get Signals". Matthew
You can get reports when running the VTR synthesis flow. Yosys does not dump reports. We will work on adding a stdout log file for Yosys. For reference: Verilog Synthesis on EDA Playground (1 of 2)
Wow, this Verilog tutorial is in HD. Nice job moving Verilog into the 21st century :)
Love EDA Playground and the tutorials and videos! Great resource! Thanks Victor!
I like that I can edit the code during/after the Verilog tutorial. Nicely done.
I just want to say thank you for putting up this website! I found it really useful!
Glad you found EDA Playground useful. Let us know if there are any enhancements/features you'd like to see.
really nice explaining, one of the best tutorials on verilog. gret work!!
this is awesome, one of the best verilog tutorials i've seen
This series is great and thank you so much for uploading!
Verilog newbie, thanks so much for your tutorials, they helped me a lot:)
EDA Playground is awesome! Thanks!
Hey cool Victor! Nicely done - and HD at that - awesome!
uuugghhh the way you people make tutorials do u ever review them?
Great tutorials! Very nice tool!
Thank you Sir , wish you all the best
Recommend viewing in 720p quality or higher.
I can say that it's not enough. Only 1080p :)
great explanation!
Really well done series! :)
You are amazing!
Hi Victor,
Thank you for a fantastic introductory video. I have a question: How does changing the T flipflops to trigger on the negative clock edge cause the counter to count upwards? I thought negative edge vs positive edge wouldn't matter because in the end, it just acts as a trigger to flip the value of the input q. I think something else is happening here.
You're right - something else is happening here.
If this circuit were synchronous, then changing the clock edge would just change the clock edge on which the counter outputs changed. It would not change the direction the counter counted in.
But this circuit is not synchronous: a ripple counter is not a synchronous design. For a design to be completely synchronous, all the flip-flops must be clocked all the time from the same edge of the same clock. This is not the case here: each flip-flop is clocked by a different clock - the output of the previous flip-flop.
Matthew
not Victor
Victor made the video and created EDA Playground. My company - Doulos - acquired EDA Playground last year and now operates it and maintains it.
i believe it is correct that on negative edge of reset, the counter will work as an UP counter. This is what happens when you build a ripple counter using JK FF as well. for reset = 0(negedge) --> UP counter, for reset = 1(posedge)--> DOWN counter
Hi. Great video! i wanted to know if theres a differnece in [3:0] and [0:3] in defining a variable in verilog. both essentialy define a 4 bit variable.
[3:0] and [0:3] both declare a 4 bit variable in verilog, as you say. The only difference you would encounter is if you tried to access a subset of the bits, for example individual bits. Then with a variable declared [3:0] the left-hand bit or most significant bit (MSB) is [3], whereas with a variable declared [0:3] the left-hand bit or MSB is [0].
Matthew
Thanks for the great tutorial. Unfortunately very hard to read if listening in with mobile phone.
Hi sir, Can I do the same hierarchy design using vhdl on EDA playground?
I've replied to your question on the EDA Playground forum.
HI thanks for videos, I am doing FIFO using edaplayground , and would like to see internal signals in waveforms , could you please let me know how to see those
Make sure you have ticked the box "OPen EPWave after run". If you're using VHDL, that's all you need to do. If you're using Verilog/SV, you need to add "$dumpfile("dump.vcd"); $dumpvars(1);" to an initial block in your testbench. Then, after you run the simulation, the waveform viewer opens and you can add signals by clicking on "Get Signals".
Matthew
How can you get a synthesis report through EDA? i tried but i dint find anything useful in the downloaded files... could you please help me?
You can get reports when running the VTR synthesis flow.
Yosys does not dump reports. We will work on adding a stdout log file for Yosys.
For reference: Verilog Synthesis on EDA Playground (1 of 2)
EDA Playground Will i get a power report too, in the synthesis report???
Padmaja g v Not 100% sure, but I don't think either VTR nor Yosys create a separate power report right now.
Is there any link where I can download verilog??
anthony amador
Hi Anthony,
Yes - the link is: www.edaplayground.com/s/example/351
Cheers,
Matthew Taylor
Really well done series! :)