I can't overstate how concise your videos are. I also like how you independently explain everything for both Verilog and VHDL, allowing us to safely skip whichever language we're less interested in. Thanks for making this high quality content!
When this project goes through the synthesis stage, iCEcube2 shows SB_DFF = 13 uses, SB_DFFSR = 18 uses, and SB_LUT4 = 44 uses. Does this mean, in total, 75 of the ICE40-HX1K’s available 1280 logic cells are used? Or is it just 44 logic cells, as each cell shares a LUT and a DFF?
Hey mate! I have a few questions. 1. Why are you using a clock here when the outputs don't depend on the rising edge? 2. Is the clock optional? 3. Can't we directly assign the Hex values to o_segment in the case statements? Why do we need a r_hex_encoding signal here?
I've followed this video and used almost the exact same code that you have. Everything works 100% perfectly, but the problem is that my 7 segment always starts at 1. I was only able to get the hex to start at 0 after I changed the line: (if w_Switch_1 = '0' and r_Switch_1 = '1' then) to (if w_Switch_1 = '1' and r_Switch_1 = '0' then) which switches from a button release to a button press input. I've went through every if statement, but can't figure out why the counter is incremented even without an input (even when I removed the input pin so that there were no possible inputs unaccounted for). Any thoughts?
I tried adding a reset key to code but was unable to have it work. Can you guide on what the syntax should look like? if (r_counter_key == 1'b1 && counter_key == 1'b0) // Falling Edge begin if ((r_counter == 9) || (r_reset_key == 1'b0 )) r_counter
You could. But VHDL is strongly typed so you couldn't assign an X"7E" to a 7-bit register without the compiler complaining. You would have to do "1111110" which I thought loses a bit of meaning. Verilog doesn't have this "problem"
These are good videos but it seems like you very rarely have a block diagram showing the modules and how they are connected to the top and that is unforgiveable.... sorry bud. I guess thats kind of good since you have to make them yourself.
I can't overstate how concise your videos are. I also like how you independently explain everything for both Verilog and VHDL, allowing us to safely skip whichever language we're less interested in. Thanks for making this high quality content!
yay! got both segment displays to count from 00 to 99 and reset. these tutorials are awesome!
Oh.. That is a great way to build my own project. Thanks for the idea!
When this project goes through the synthesis stage, iCEcube2 shows SB_DFF = 13 uses, SB_DFFSR = 18 uses, and SB_LUT4 = 44 uses. Does this mean, in total, 75 of the ICE40-HX1K’s available 1280 logic cells are used? Or is it just 44 logic cells, as each cell shares a LUT and a DFF?
So the 7 seg display on the Go board is common anode? That is the reason for the inverted output values?
you are a good man.
could you make videos about FPGA Programming : Encryption & Decryption ??
On your Go Board, is the decimal point on the seven-segment display connected to any of the FPGA pins? It isn't defined in the constraints file.
No it's not.
Hey mate! I have a few questions.
1. Why are you using a clock here when the outputs don't depend on the rising edge?
2. Is the clock optional?
3. Can't we directly assign the Hex values to o_segment in the case statements? Why do we need a r_hex_encoding signal here?
Good question, yes you're correct that this entire module can be done without a clock. It's just a bunch of Look-Up Tables (LUTs).
Thanks for the quick response. Could you please respond to my 3rd question too? Thanks
For #3, you could directly assign, but that would require more code and not be as clean, in my opinion.
I've followed this video and used almost the exact same code that you have. Everything works 100% perfectly, but the problem is that my 7 segment always starts at 1. I was only able to get the hex to start at 0 after I changed the line:
(if w_Switch_1 = '0' and r_Switch_1 = '1' then) to (if w_Switch_1 = '1' and r_Switch_1 = '0' then)
which switches from a button release to a button press input.
I've went through every if statement, but can't figure out why the counter is incremented even without an input (even when I removed the input pin so that there were no possible inputs unaccounted for). Any thoughts?
I tried adding a reset key to code but was unable to have it work. Can you guide on what the syntax should look like?
if (r_counter_key == 1'b1 && counter_key == 1'b0) // Falling Edge
begin
if ((r_counter == 9) || (r_reset_key == 1'b0 ))
r_counter
Hi there, why do make the hex encoding register an 8 bit value if we only use 7 of those bits? Is it not possible to do "6 downto 0"?
You could. But VHDL is strongly typed so you couldn't assign an X"7E" to a 7-bit register without the compiler complaining. You would have to do "1111110" which I thought loses a bit of meaning. Verilog doesn't have this "problem"
ok! thanks for explanation
-- Do not forger to put this onto your final code in case statement:
when others => null;
These are good videos but it seems like you very rarely have a block diagram showing the modules and how they are connected to the top and that is unforgiveable.... sorry bud. I guess thats kind of good since you have to make them yourself.