Thanks for your kind comments. I just hope more people subscribe to my channel and get benefited with the efforts and enhance their learning experience.
The videos have been incredibly helpful for my studies, and I’m very grateful for the support they’ve provided. I have one question. When attempting the stability simulation shown at 37:28 in the video, if the frequency sweep range is extended down to 0 Hz, mu drops below 1 at around 20 MHz, while mu prime falls below 1 only at DC. Doesn’t the fact that mu drops below 1 at low frequencies indicate the possibility of oscillation at low frequencies?
Firstly, thank you for this tutorial video. I have some issues: 1) Could you turn on Subtitles (Auto Translation) for this video? Sometimes I can't hear clearly what you said. 2) What is the main purpose of Step 4_Bias Network Design and at 41:38? 3) What is the function of MSTEP, MTEE_ADS, MGAP ...? What happen if we don't use that components for modeling? Sorry if you explained this in the video but because of 1). Thanks you so much again.
I can hear the audio properly, may be you can check your headphone/speaker settings. I tried to switch on Auto Captions, you can try to see if it works for you.
please explain how to calculate the width and length for the quarter-wave MLIN block in Step 4 that is connected to the Microstrip Tee. I don't get accurate results with my calculations for its length.
Very good explanation sir,plz continue to share technically good stuff and present on different rf products like mixers,pa,filters,...design it will be help full to all
I didn't understood the question completely. Class-A operating point is in kind of middle of your Ids-Vds curve on a specific Vgs value for the FET and that's how I picked it. Does it help to make things clear?
thank you for video. sir i have one doubt that if i have a datasheet of gan HEMT and want to use in ads then you told we can use it through s2p. but i have doubt how to assign gate source and drain terminal to that box(snp) or how i understand which terminal is gate source drain (like there will 1 2 and ref terminal.).
Its usually provided in the header of the S-Par file. However, the typical normal is 1: Gate, 2: Drain and 3: Source (reference) for all HEMT or FET devices.
Hi.. thanks for this helpful video,... i have a question if we are going to design a cmos amplifier with many transistors and resistors, etc...., how can I simulate it (with a model)
Thank you sir for such detailed videos on RF Circuit designing. I designed the LNA circuit mentioned in video but got "Warning detected by hpeesofsim during netlist flattening. Resistor `A1.RSSP' is shorted." this as warning because of which results are not coming. KIndly help.
Hi, This warning is not normal but your results won't be affected by this. You need to check for other issues to figure out the problem with your results.
Hi, I think I explained that during relevant section. Kindly listen to that section again but here is the quick comment: Its is open circuit stub so it provides short at connection point in the lamda/4 bias line which gets transformed to Open circuit in the bias line to avoid leaking desired RF into the bias line. This is optional and not mandatory but if you don't have it then you need to be careful about compensating for the delta electrical distance caused due to the decoupling capacitor mounting pads etc because ground/short is available on the far end of these capacitors which you are utilizing to realize the open circuit for desired RF freq with lamda/4 line. Hope this helps...
Thanks Sir, I have another question! In your biasing line design, it is terminated with two terminals 50 ohm and provides good S11 and S21. But the impedance at input and output sides is not 50-50 Ohm because input and output impedances of the device are not 50 ohm, whether the biasing network works well? or how to ensure open circuit for the biasing line with such the impedances.
@@annguyendang8388 Biasing network is being analyzed in reference to 50Ohm to make sure it works perfectly on its own and be as transparent as it can be. It necessarily has nothing to do with matching network which you will have to match the transistor impedance to 50Ohm. However, in some cases like in PA output section you may include it to be part of the output matching network. Eventually, when you design matching network, you look at cascaded impedance for device + bias network and that becomes your impedance matching network design goal. Hope this helps in some manner.
sir, Thank you for bringing this channel. you have given very good tips which we do not find in the text book I have simulated LNA using BJT and tested the board . can you talk more on the different biasing circuits and how to choose them.
Hi, Thanks for your feedback. Hope your LNA worked the way you simulated, let me know the outcome or comparison between simulated and measured if you designed it after watching this video and following all the steps explained?
Hello Mr Anurag. Pls guide us as how to go about designing an amplifier(low noise ) to detect a microvolts signal in series with a resistor .The design should be at 10KHz.The desig and simulation in ADS.
Thanks for your enthusiasm. I mean how can I get the Part1, Part2 and Part3 folder at Workspace (like at 20:28)? I will need to do it by myself or if you have links to download it?
I have created step by step tutorial with step clearly explained and demonstrated so that designers will be able to do it on their own by putting their own efforts...😊
Hello, Thank you very much for this valuable tutorial. I have an S-parameter model of a transistor and not the device model. now I am wondering how to bias the model and adding transmission lines to create lambda/4 and other lumped components. as I see here, we need a bias circuit to connect to Gate and Drain nodes. while in an S2P block, I don't know how to implement this. finally, I want to generate the layout for fabrication but I don't know what is the starting point in this case ( S-parameter model) again thank you for your hints and helps
Hi Ehsan, Process will be exactly the same with no change at all as shown in the video. Only difference would be that your circuit performance won't change if you change the bias voltage as you have only S2P file and output power will never compress and it will keep on increasing so there is no fun in doing HB simulation. You can skip the DC IV simulation part and go directly to stability analysis using the S2P file you have. Make sure S2P does have noise data else you won't be able to see Noise Figure which is important for LNA. You should still design the bias network and attach it to rest of your circuit. Port1 of S2P file will be gate (or Base for BJT) and Port2 will be Drain (or Collector for BJT).
@@BhargavaAnurag hello Anurag, Thank you so much for information. I am working and studying on your design. Everything is ok so far, just i am a bit confused on the bias network cap section at the end of it where you have some pads and a capacitor parallel to it . Is it a kind of special thing ? I have seen different bias networks as chucking RF. Is there any hint or book for this area to read more and understand more to manipulate such designs ?
The video is very good and helpful. However, I would like to ask about the bias network. You mentioned earlier using 105 ohms impedance and 90 degrees. Can this method also be used for power amplifier design, or is it only applicable to LNA?
You could use similar approach for PA input bias, but you need to pay attention to output bias section as per the dc current and it may not be possible to use high impedance line due to high drain/collector current.
Hello! thanks for your work, my i askyou.. while running the same circuit in my computer i dont get any of the mu or muprime graphs... why that could be? Thanks
Hi Sergio, I am not sure why that might happen but I know one of the ADS version had a bug for the same. If you use newer/latest ADS release, it should all work fine for you.
@@BhargavaAnurag Thanks for your time answering my question. I just found it was because i had to create the chart in the first place and then select the parameters to load in (Mu and MiPrime). Have another question if you have the time.. Im trying to design a RadioTelescope as my final project for my engineering degree, right now i cannot find the same transistor as you are using here, but limited to some NPN BJT i can find. Do you have rocomendations about the topology? or different steps to do the analisis for the LNA? Thanks again for your time. BTW using ADS 2016
@@sergioruppel7269 You can get the transistor I used in the library provided in the ADS: C:\Program Files\Keysight\ADS2016\oalibs\componentLib folder. Copy the RF Transistor zip file in your project folder, unzip it and then add this design kit like any other library in ADS and you should be able to get ATF21170 transistor for your use. You can see how to add vendor components from this video: ua-cam.com/video/Vf6dVKLxe4M/v-deo.html Topology using NPN BJT will also be very similar except that you will use a current source in the Base instead of a voltage source like I used for the FET device.
Hello Anurag, Thanks for sharing this video. A quick question, Series Resistance at the output will cause a drop in gain like you said. You still kept the 20 Ohm resistance at the output while introducing the shunt RC network. Can't we just remove the "R" at output and tune the input shunt RC network for stability?
If you can achieve stability with only shunt RC then why not. However, that may be but difficult and eventually you will need to lower shunt resistance value and you will see similar loss. Putting series resistor in output is not all that bad as long as you do proper analysis to achieve required gain that you are looking for. It all depends on the device characteristics so designer will need to play with all the possible topologies and pick the one that gives best results.
Thanks a lot for this tutorial, I could not figure out how the 90deg and 50 Ohms became 1.1 width and 19.8 length. I have used LinkCalc and the result was 18.6 length and 1.07 width, ??
I checked the dielectric parameters carefully and test both results, Your results was the most suitable to the case, even the linkcalc was not the same Most of thanks,
Great Video. Sir please help me how to import the PDK file into ADS because it always shows the warning or error invalid lib path. How to remove the error or import the PDK into ADS.
Hi Hung, I am glad you liked the presentation. Unfortunately, there are no slides for you to download as of now. You can pause video at every slide and take snapshot to create your own copy. Hope this helps in some manner.
Hi Ali, Please refer to videos 41-43 under Learn ADS in 5mins playlist to get full context of it. For via array, you simply draw 1 VIA of desired diameter/radius and then use Edit->Copy/Paste and select option of Step & Repeat to enter X & Y values etc... Hope this helps.
Hello Sir Anurag ! Hello everybody ! Need help on the following I setup s-parameter simulation of ATF-21170, i get a warning message "Resistor A1.RSSP is shorted" why this warning is appearing ? and how to remove it ? Commnet please
Thank you for this perfect tutorial. I didn't understand a point in Step4 bias NW. There is DC_Block just after TermG1 in schematic design, but you didn:'t put the DC block just after the Termg1 in the step4. So when you feed the circuit with DC_feed from the point between the MSTEP and MLIN-TL4, wont the DC current flow throughout the MLIN TL1 to the TermG1?
Hi Sabri, Kindly have a look again and you will get answer. There is coupling capacitor between DC bias point and the Termination both at input and output side.
Hi Amith, You just need to remember that you have to isolate DC and RF in the DC bias section and the prime objective to let DC pass and block any RF energy so you pick a choke or inductor that can give you SRF around your RF as at SRF (Self Resonant Freq) it will have parallel resonance offering the best possible resistance to prevent RF leaking into the DC section, other factor includes to have low ESR to avoid DC drop etc. But some people make it part of their matching network criteria change a little bit so its subjective to what topology you want to work with. Similarly, DC blocking Cap commonly referred as coupling capacitors in the path of RF ideally should have SRF (Series Resonant Frequency) at RF frequency to give you least resistance in the main path but then it all depends how you decide to use this as some time we use it as part of the matching network (like I did in LNA video) then you go with any value suitable for matching application to kill 2 birds with single stone. Prime objective is to block the DC which any Capacitor value will do and then whatever other purpose you may want to use it for and then come up with value accordingly. Look for some App Note on this topic for more details, I remember there were some nice ones from MACOM, NXP etc Hope this helps....👍
Thank you, Sir for this wonderful lecture and covering the complete design strategy of LNA. Unique to this content is the stability network design. Because in most texts on LNA design, impedance matching of the active device under unconditionally stable condition is shown and not the strategies on the stability network. Therefore, you are right when you mentioned that this material is 'not available elsewhere' in the Introduction slide😀. Do let me know if this perspective is correct. Sincerely, naive MMIC designer
Hi Rahul, You picked up one of the many good points which aren't discussed in many books. Watch both of the LNA tutorials carefully and you will find many other points/topics like Stability...😊
Sir, you already told that you'll upload the full tutorial to design a broadband RF power amplifier including load pull, source pull simulation to determine optimum load & source impedance of the transistor with the use of ADS software on november. But still there is no tutorial about it. Can you please do it within few days. We are really in the nead of it because of our research project.
Probably you haven't turned on the notifications for my UA-cam channel. I already post 2 videos on PA design and will post the final one next week. Kindly check Tutorial 16 and 17 under RF Design Tutorials playlist and for future make sure notifications are switched on so that you are always notified about the new video uploads...
@@BhargavaAnurag Thank you sir with regards to a project I am working on and I am currently stuck, I would like to reach out to you by mail or by any means... How do I contact you please?🙏
hellow i have some problem in first step when i show the characters of the transistor and run simulation this message appear Warning detected by hpeesofsim during netlist flattening.Resistor `A1.RSSP' is shorted.' please help me..
Great Explanation! I wanted to design the LAN by "hand" with some python scripts and smith chart but did not had the whole overview after reading books and application notes. With your explanation its much clearer now.
Hi Karanam, As you can see I haven't used any equations during the design process. You need to apply fundamentals and if you want 2GHz wide BW LNA on 2 GHz center frequency that is 1 octave BW based design so might be quite difficult on a PCB and MMIC might be more suitable process for the same but again it depends on what specification you are looking for. Its all about Broadband matching network design and whether selected transistor gives you good enough parameters to design such broadband LNA. Check out Broadband Impedance Matching tutorial video to get some more understanding....
Sir, after I unzip the design kit and click ok when the dialog box appears if I want to add, there are no libraries or schematic added to my workspace. What should I do?
not sure what you are doing wrong. Kindly contact your local Keysight tech support team to show the problem you are facing and they can offer solution.
sir! does microstrip line technology is easy process to do? because I'm as a engineering finale year student, doing LNA design for the 1st time...in ADS as you shown in this video. Is it achievable?
Hi Prasanna, Microstrip is the easiest printed line process. Whatever I showed you in the LNA design is surely achievable and I talked about all practical considerations that you need to take during the design.
Hi, You don't need to download the kit that I mentioned in this video. All the components can be found under the ADS installation directory e.g: C:\Program Files\Keysight\ADS2021_Update2\oalibs\componentLib If you are looking for any newer vendor transistor kits that is not available under these libraries then you could visit respective vendor's website to look for the models. Hope this helps.....
Hi sir, I am designing lna for 2 ghz using NXP BFU690f rf transistor. I downloaded s2p files it contains data of signal to noise ratio files and not including the signal to noise ratio files also. Which file has to used for designing.
Sir, Thank you for giving a wonderful lecture video. This helps very RF engineers and academicians to know LNA in detail. I am designing a Microstrip Isolator, can u help me with how to include ferrite magnetic materials in the design? Give some book references for the design.
Excellent tutorial sir. Thankyou very much sir for the lesson. Sir i was wondering if you can help me out with 2 stage amplifier design for a mmic designer.
Hi Nishant, I don't have bandwidth to support an actual design as a consultant but you would definitely find consultants in India and elsewhere to help you on paid basis depending upon scope of work. Doing 2 stage or 3- stage design is not so difficult if you keep following the fundamentals and take care of interstage matching and stability of your circuit.
@Anurag Bhargava Dear Sir, I have gone through LNA tutorial 9-10 videos but it could not solve the problem. First, you used series resistance at the input and output sides separately. Then, you deactivated input resistance, and connected RC network towards the ground. The values were picked previously and there was no information for derivation. Best regards.
I showed concept of placing resistor at different places and its impact on the noise figure so don't get confused with that. In an ideal case you can place resistor on the output side for LNA and if device is not fully stabilized then shunt resistor can be used in series to capacitor (to avoid DC) but the resistor value should be as high as possible to avoid resistive loading which will degrade noise figure so its all about balancing the different parameters like gain, noise figure, stability etc
Sir, Your tutorials are very encouraging for new learners...!! One small request, for upcoming videos, if possible please provide links in the description for previous video tutorials wherever you are mentioning it in the current tutorial..
Hi Manish, I will try to do that, usually I always to one of the videos under "Learn ADS in 5mins" playlist for different videos for RF Design Tutorials and hopefully it is easier to figure it out based on the topic mentioned in the playlist.
congatulations for this topic, it is really helpfully, I am from latin america, could you recomend a book about this videos. with more detail because some parts i cant understand clearly.
Hi, For normal Amplifier technology and theory, you can always refer to books like Gonzalez but those books don't talk about the practical implementation of the amplifier which I tried to cover in the video but if you want to understand the theory and concepts then those are excellent...If you have any specific query then you can post them and I can try to answer those.
Nice video... But problem here on adding the library to the workspace, it says "Error reading library definition file "C:\Users\italo\MyFirstWorkspace_wrk\MyFirstWorkspace_lib\RF_Transistors_vendor_kit\lib.defs" Library definition could not be found" What should I do?
Hi, It seems you unarchive the transistor library inside the workspace library which is not good. Kindly unarchive it somewhere else and then add it to your workspace. This should resolve the issue for you.
@@BhargavaAnurag Sure thank you! Do you have any tutorials about including a new part on ADS (or edit), I am struggling on that? Although, I am trying to simulate the ATF34143 (I found an .zap file) and I am trying to create the matching circuit (it is possible to give me the capacitors, inductors, or resistance on the input and output?), SNR analysis, noise, gain, and some graphics... It would help me a lot! Regards!
Kindly don't mix up the things. ATF34143 model should be available inside the RF Transistor library and you should be able to place it on your schematic after including the library and proceed with your simulations by watching different tutorials I posted. zap file which you mentioned is a old style zip format used by earlier ADS versions (but its not a component library like RF Transistor). You can unarchive the zap file by going to ADS Main Window->File->Unarchive and then browse to this file. After unarchiving you would be able to see the contents inside, it might have an alternative model representation for ATF34143 transistor and if you want then you can use the same for your simulation and impedance matching applications. Hope it is clear....
@@BhargavaAnurag Sure is it clear now thank you for your attention Anurag! I am actually seeing you 5min tutorials and looking for my necessities (how to create a new match I/O circuit for amplifier, but still some doubts about intrinsic impedance on the point of view of source or transistor, the s-parameters and etc), I am more familiar with the Capture CIS and PSPICE for simulations. Anyway I am searching this kind of contents and appreciate yours either!
To find impedance of an active device, gain circle, noise circle etc you can watch this tutorial: ua-cam.com/video/pNSPMPPHagQ/v-deo.html Again, be careful in your choice of words, intrinsic impedance of a device is different from input and output impedance. Intrinsic impedances, voltage or current is very dependent on the kind of model vendor provides you and may not be available in all models, I have only seen those in High Power devices meant for PA applications. They are largely used in PA designs to look at intrinsic node Voltage and Currents, Dynamic Load line etc but for impedance matching kind of application for a LNA or normal amplifier what you need is normal input and output impedance which is quite easy to find using S-Parameter simulation once you watch the above video but you need to make sure you bias level of the device is set properly and make sure right bias network is designed as all of those things will affect the impedance that you see at the input & output. Take 1 step at a time and you should be fine, when you look at the LNA video see how we took 1 step at a time and were successful but in order to do those watch 5mins tutorials to pick up necessary skills to be employed in an actual circuit design. Hope this helps
Hi Sir, thank you so much for these tutorial videos. If I may, I have a question. Would you not need a T-junction component in the schematic when adding the radial stub at the time-mark 50:20? Thanks beforehand!
Yes, if you are using a radial stub in shunt then it is recommended to connect a MTEE there but it is not going to be a big problem even if you don't connect it as your RF will be largely isolated at that point.
Hello, this very a good tutorial. I'm designing a low noise amplifier too and it's very difficult because I usually don't use ADS software. Do you also provide services for people who want to design and simulate LNA with ADS software? Thankyou..
Thank you Sir for the remarkable effort and exceptional content. Just one question: our frequency is 2.4 GHz and therefor lambda=124 mm and lambda/4=31 mm, your design is 100% correct but I can't understand why the quarter wavelength line's length in your design is 19.8 mm.
I ask another question, i have to go back and forth with my design. i achived stability with my particular bias network and transistor but now my MAG is around -1.7 while it was around 20dB with the previous bias network (but unstable).. do you have a tutorial to design the network to optimize for gain with an stable system? thanks
I am not sure how gain can drop from 20dB to -1.7dB and this indicates there is some problem in the way you configured your network. Whatever I showed in this video is to stabilize device first as well as keeping an eye on the Gain as well. Kindly relook at your design and hopefully you will be able to figure out the root cause of the issue.
It is available at the link provided in the video description. To download the workspace, you need to be a valid Keysight customer and create a Knowledge Center login account for yourself. Please contact your local Keysight tech support team for help.
Hi, I am not sure what you meant by explaining the lamda/4 practically? I showed the same in Part2 of the video in EM-Circuit excitation section. Please watch it to get more context or just use Smith Chart tool in ADS to see how lamda/4 behaves. Put Zs or Zl as 0 or 9999 and then use a transmission line and see what happens if you insert a 90deg line i.e. lamda/4. For 23-30 GHz, I am not aware of any discrete transistors available. Best I have seen is till 18-20 GHz, www.mitsubishielectric-mesh.com/products/pdf/mgf4965bm_1211.pdf Beyond 20GHz, your board and assembly parasitics will be too hard to contain and it is recommended to design using a suitable MMIC process. Hope this helps in some manner...
Thank you? Could you help please? You are said, that frequency is 2,4Ghz and lambda/4 line is 19.8mm? How is it possible if lamda for 2.4GHz is 0,125m? 0,125m/4=0,031m
I am not sure which formula are you using? Try this: lambda (in mm) = 300/(freq_in_GHz*sqrt(Er)) so if you take freq as 2.4 GHz and Er=4 then the calculation will be: Lambda (in mm) = 300/(2.4*sqrt(4)) = 62.5 mm i.e. lambda/4 = 62.5/4 = 15.625mm Hope this clarifies...😊
Hi Anurag, I think it is important to mention that noise fiqure is strictily defined as the ratio input SNR divided by output SNR when input noise temperature is 290 K. Otherwise, great video!
Good point...refer to the video at 27:17 and you will realize that it was covered...😜 Thanks for the comment anyways and hope you enjoyed watching it....👍
Please sir, is it possible to build a network of LNA(5.5GHz) and IF amp(300MHz) together in single circuit just like the circuit you have while doing the recap of LNA( that contains antenna and mixers)? If yes, please sir how can one go about it sir? Thank you in advance.
Very useful video again from you. Thank you so much for those practical tips. One comment: I felt that you could have explained DC bias network creation more in detail :)
@@BhargavaAnurag Appreciate your tutorial. These are questions I had: 1. For i/p, o/p microstrip in bias n/w, you mentioned 1-2mm length with 50Ω would be fine. So that will give around 40deg phase shift to input signal based on line calc result. Is that okay ? 2. You were saying 105Ω would be fine for lambda/4 line. I understand it wouldnt get too hot as FET will be drawing less current. But how would you know what is optimum impedance and how hot this microstrip would get ? Is it to be verified with 3D simulation ? 3. Doesn't Mstep add any electrical length to lamda/4 line before it ?
@@satyat7051 Here are my comments to your queries: 1. There is no concern if these sections provide 40deg or whatever phase shift as we can always do the matching network according. Also, 1-2mm is a typical/general guidance and you need to know your own fab requirements to make sure components can be soldered, leads can be mounted etc. 2. More impedance the better to block the RF frequencies. There is no special need of 3D simulation, you just need to compute current carrying capacity of a Microstrip line as per the width and these formulas are there in any Microstrip text books like T.C. Edwards etc. 3. Mstep is only to account for discontinuity effect due to different widths at the junction and has an insignificant contribution to electrical length.
Anurag Bhargava thank you for clarification. I will refer to the text book that you mentioned. I am interested to relate temp Vs current on microstrip line. . Again, Your tutorial is amazing :) I hope to see PA design also from you.
It seems to be a low noise transistor for LNA applications. If so, you don't need a full non-linear model and you can design LNA by just having S2P file with noise parameter data that transistor vendor can provide to you or it might be available on their website
This is such a well organized video. Like you rightly said, text books are so voluminous that reading the details we can't easily get the design concept. I hope you continue making such videos for the benefit of the community. Hats off. Just one question. If I decide use a FET on a CMOS process, will the same specifications (NF, Gain) that you've showed here provided in the PDK?
Loved your comment...!! Thanks for providing your feedback. For CMOS, you will have MOSFETs instead of FETs and NF will not be as good as what you see here because Silicon is a poor quality i.e. Noisy substrate for LNA and that is why mostly you will use Low Noise GaAs pHEMT process for LNA designs. Using CMOS PDK transistor models you can always find out the NFmin, Gain etc as shown in the video for sure... Silicon is quite a cheap & abundantly available material compared to GaAs plus you can have RF & Digital circuits on a single chip to design a complete SOC (System on Chip) for a Transceiver system. In practical systems such as Mobile Phones, you always have RF Front end module (known as RFFE modules) where PAs and LNAs are designed with GaAs processes, Switches using SOI and tons of SAW and BAW kind of filters for various bands etc) followed by Silicon-based Transceivers or Modems. Each technology has its pros & cons as you select the implementation based on the specification & size constraints on hand...!! Hope this helps in some manner....
@@BhargavaAnurag Thank you very much for a detailed and insightful response. I was curious of the question because I did my PhD on process engineering applied to LNAs on PD-SOI substrate. And because of specially engineered Trap-Rich SOI substrate, substrate effects can be significantly reduced compared to CMOS. From what I understand, heterogeneous integration is what is preferred for RF frontends incorporating different technologies. Also, what is your opinion about future of SOI? In my literature review, I found some examples of devices which I thought had really good noise performance. How does it compare to GaAs pHEMT? ieeexplore.ieee.org/abstract/document/7874382/ ieeexplore.ieee.org/abstract/document/8439132/
Hi Arun, Thanks for pointing me to these references. I don't have much experience with these new processes as of now and looking at the current trends followed by major companies I can tell you III-V is still the preferred choice for LNA as well as PA and SOI is very popular for Switches in the RF Front End modules. But again its always good to be in know of the newer & upcoming technologies.
Its already included in the ADS library. Watch video carefully again on how to add this library in your workspace else this video 9 & 10 will help you as well: ua-cam.com/play/PL9OnCetH8TYrWFGB4QkDP8HVaY-Aum6Hc.html
Sir I am quite new to RF design and trying to design for my university project. So this is my question. 1. i am designing push pull class B amplifier in frequency of 1GhZ below. Is it necessary for me to create Bias network design to replace the dc and rf choke ? 2. If it is not necessary, how to know the right value for capacitor and inductor to put in my dc block and rf choke? Any formula? 3. For the Tlines that connecting to each devices, what is the rule of thumb (range) for choosing the length and width of each T line.
Hi, For freq below 1GHz, you don't need to use MLINs for bias network as you will easily find chokes/inductors for RF blocking purposes. Kindly google for app notes from vendors like NXP and you will find good papers on the same.
hi sir....tutorials are very useful....i have doubt sir,....How to convert lumped element to microstrip.. inductor converted to microstrip and same as capacitor....
Hi sir, its wonderful lecture with excellent pronunciation... You have used pf_hp_ATF21170_19931015 GaAs model transistor to design the LNA... Can you tell us which model is best for GaN based LNA..? Thanks, Naresh...
Hi Naresh, I don't think there is anything called GaN LNA as GaN is known for high power application and not for low noise. For LNA, GaAs HEMT is still one of the best technology to use. ATF21170 that I used is a pretty old device, now a days there are much better low noise HEMT technologies available.
Sir, my work is based on GaN HEMT device to design an LNA. But, searching lot to select a model for GaN... So, asked you for help. Thanks anyway for prompt response... If you know model for GaN, please let me know...
@@souparnika6931 I would seriously advice you against pursuing this work & I am not sure who gave you this work? Due to the reasons I mentioned before GaN is a high power process and it provides high bandgap devices for high power application and noise is the least concern when you deal with those devices but if you are lucky to find a GaN device whose NFmin is < 1/2 of your target LNA circuit noise figure then ofcourse you can go ahead and design LNA.
Sir ,I have one concern ,at mmW frequency ,what type of resistor should be used for providing stability of the device..can be use thin film resistor or simple resister of 15 ohm..?
I have seen some thin film resistor in TLine microstrip pallete..there is given some equation...RS( freq)=Rs√freq..how to use that equation at higher frequency??. according to that equation sheet resistance may vary at higher frequency...I don't think show ..it may not give a good agreement between simulation and measurement results..
Hi Saurabh, For thin film at such high frequency, I wouldn't recommend to use schematic model. You should define the correct stackup with correct material properties in layout and then create a parametric EM component for yourself to be used in your design.
Hi Mawuli, You don't need a tutorial video for this. Here are the simple steps: 1. Define a variable on schematic e.g. myCap = 1 2. Assign the variable to the capacitor component on schematic which then might look like: C=myCap pF 3. Setup and run the parameter sweep 4. Insert the graph and select StabFact and click on "Add Vs" and then select myCap from the available options 5. Now you will have the plot of K vs. myCap as you need. Hope this helps
@@BhargavaAnurag Got it!! Great, in fact, I don't know how much I should thank you but I believe you shall surely reap the fruits of your kindness in the land of the living!
Hello sir. I need to design a broadband LNA that covers 1-6GHz frequency as I am replicating a competition paper where they had used TGA2602 SM (Qorvo) transistor in cascade (the concept was consume more dc to achieve broadband performance) but transistor ADS deign kit and its equivalent model is not given by Qorvo and S2p file contains data without Noise data. We discussed about that in comment section as well. So, I need to go for replacement transistor. Can your please suggest me a replacement transistor that can be used for broadband LNA design and also its ADS model will available by vendor's. The design specs are: broadband LNA (1 to 6 GHz), Gain: 13dB, Noise Figure
Hi Adnan, You should be able to find suitable transistor from other vendors or from Qorvo themselves and you can always request them to give S2P file with Noise data. You need to do literature search and look for devices from Infineon etc
@@BhargavaAnurag Yes sir I have found an RF BJT transistor from Infineon and few from other vendors as well and their design kits are also available on ADS. Can you please guide me if I want to achieve a broadband bandwidth of more than 3 GHz for an LNA what approach should I adopt. Please guide me in context for achieving broad bandwidth
You don't need to bias anything in that case but you still got to design the bias network in schematic and layout to make sure there is nothing wrong with the overall design and impact on the RF performance.
@@BhargavaAnurag Thanks so much. Watching your videos systematically. I have another question: Do you apply both gate voltage and drain voltage or just the drain with S2P?
SNR can't be simulation in S-Parameter directly as such. You don't need it for LNA as you can directly see Noise Figure which is what you care about. SNR is usually seen on Modulated Signal level....
@@BhargavaAnurag Thank you so much sir... actually I was having the internship under DST-SERB-ECRA at NIT WARANGAL...so there I have to design a LNA of gain 30db
Great video as always Anurag, thanks for helping so many people in this interesting topic. Can you comment on (or give references to) why the shunt/series impedance improves the stability of the device?
Hi Miguel, Thanks for your kind comment. For understanding how resistors improve the stability, you can refer to causes of Oscillations in a transistor & find out how to do oscillator designs and do exactly the reverse in amplifiers to prevent that a.ka. break the loop gain chain which might induce positive feedback....😊 In simple words, while designing amplifiers we need to dampen or kill the oscillations caused due to L & Cs and resistors are the perfect components to do that. Different devices work differently hence we need to try different values or topologies to achieve our goal. For more details, refer to this: www.mwrf.com/technologies/components/article/21846567/ensure-stability-in-amplifier-designs
Sir, can I get the license of ADS for myself ? Without involving institute ? As most of the content on Keysight website get restricted when I select my country.
One of the best few channels on youtube for the subject. there aren't enough good rf channels. thank you.
@@hyperelectron-tg5cz thanks for your kind words…👍
Thank you for contribution to science and engineering. I truly appreciate you doing this.
Thanks for your kind comments. I just hope more people subscribe to my channel and get benefited with the efforts and enhance their learning experience.
I have Designed RF PA using ADS ...refreshed my memories regarding ADS . Thanks for Sharing
You are most welcome
Thank you so much! I need to listen to this again because there were many things pointed and it is totally worth the time spent. Much appreciated!
Glad it was helpful!
Can't thank you enough Sir.
Haven't seen this type of content anywhere.
I am glad you liked it....
Most helpful video I have ever seen on youtube regarding RF stuff. Thanks, subscribed and liked.
Welcome aboard!
The videos have been incredibly helpful for my studies, and I’m very grateful for the support they’ve provided. I have one question. When attempting the stability simulation shown at 37:28 in the video, if the frequency sweep range is extended down to 0 Hz, mu drops below 1 at around 20 MHz, while mu prime falls below 1 only at DC. Doesn’t the fact that mu drops below 1 at low frequencies indicate the possibility of oscillation at low frequencies?
Hi Anurag, You are my inspiration and my hero as far concern about RF simulations and its explanation
Thank you so much 😀
Firstly, thank you for this tutorial video. I have some issues:
1) Could you turn on Subtitles (Auto Translation) for this video? Sometimes I can't hear clearly what you said.
2) What is the main purpose of Step 4_Bias Network Design and at 41:38?
3) What is the function of MSTEP, MTEE_ADS, MGAP ...? What happen if we don't use that components for modeling?
Sorry if you explained this in the video but because of 1). Thanks you so much again.
I can hear the audio properly, may be you can check your headphone/speaker settings. I tried to switch on Auto Captions, you can try to see if it works for you.
Just one word 'Excellent'
Glad to know that you liked it...👍
Thank you very much for your tutorial LNA design. That helps me learn a lot.
You are welcome 😊
please explain how to calculate the width and length for the quarter-wave MLIN block in Step 4 that is connected to the Microstrip Tee. I don't get accurate results with my calculations for its length.
Use LineCalc in ADS. Typically 85Ohm or higher is considered to be good enough for bias line applications.
@@BhargavaAnurag Thank you for your response. I got it to work with 50 ohms back then with -37dB return loss.
47:05 I am getting a mirror image of both the graphs. Can you please help?
the best video I have ever seen , thanks
Thanks for the feedback and I am glad you liked it..👍
Really helpful tutorial which is exactly to the point on the topic
Very good explanation sir,plz continue to share technically good stuff and present on different rf products like mixers,pa,filters,...design it will be help full to all
Sure I will.. Thanks for watching...👍
Thank you sir! It is so much info and very clear. How did you pin pick class A operation point on the DCIV curve please?
I didn't understood the question completely. Class-A operating point is in kind of middle of your Ids-Vds curve on a specific Vgs value for the FET and that's how I picked it. Does it help to make things clear?
thank you for video. sir i have one doubt that if i have a datasheet of gan HEMT and want to use in ads then you told we can use it through s2p. but i have doubt how to assign gate source and drain terminal to that box(snp) or how i understand which terminal is gate source drain (like there will 1 2 and ref terminal.).
yes sir this is my doubt also.
Its usually provided in the header of the S-Par file. However, the typical normal is 1: Gate, 2: Drain and 3: Source (reference) for all HEMT or FET devices.
Hi..
thanks for this helpful video,... i have a question
if we are going to design a cmos amplifier with many transistors and resistors, etc...., how can I simulate it (with a model)
You just need to include the PDK of the transistor/process you need to use.
@@BhargavaAnurag thank you very much
this was the topic I needed. thank you so much, Great work
Glad it was helpful!
Thank you sir for such detailed videos on RF Circuit designing. I designed the LNA circuit mentioned in video but got "Warning detected by hpeesofsim during netlist flattening.
Resistor `A1.RSSP' is shorted." this as warning because of which results are not coming. KIndly help.
Hi,
This warning is not normal but your results won't be affected by this. You need to check for other issues to figure out the problem with your results.
An excellent tutorial, but I wonder that
what is purpose of using radial stub in the biasing network, Sir?
Hi,
I think I explained that during relevant section. Kindly listen to that section again but here is the quick comment:
Its is open circuit stub so it provides short at connection point in the lamda/4 bias line which gets transformed to Open circuit in the bias line to avoid leaking desired RF into the bias line.
This is optional and not mandatory but if you don't have it then you need to be careful about compensating for the delta electrical distance caused due to the decoupling capacitor mounting pads etc because ground/short is available on the far end of these capacitors which you are utilizing to realize the open circuit for desired RF freq with lamda/4 line.
Hope this helps...
Thanks Sir, I have another question!
In your biasing line design, it is terminated with two terminals 50 ohm and provides good S11 and S21. But the impedance at input and output sides is not 50-50 Ohm because input and output impedances of the device are not 50 ohm, whether the biasing network works well? or how to ensure open circuit for the biasing line with such the impedances.
@@annguyendang8388 Biasing network is being analyzed in reference to 50Ohm to make sure it works perfectly on its own and be as transparent as it can be. It necessarily has nothing to do with matching network which you will have to match the transistor impedance to 50Ohm.
However, in some cases like in PA output section you may include it to be part of the output matching network. Eventually, when you design matching network, you look at cascaded impedance for device + bias network and that becomes your impedance matching network design goal.
Hope this helps in some manner.
thankiuuuuu, fromm VietNam with love, that's an amazing video
Glad you liked it!
sir, Thank you for bringing this channel. you have given very good tips which we do not find in the text book
I have simulated LNA using BJT and tested the board . can you talk more on the different biasing circuits and how to choose them.
Hi,
Thanks for your feedback. Hope your LNA worked the way you simulated, let me know the outcome or comparison between simulated and measured if you designed it after watching this video and following all the steps explained?
Hello Mr Anurag.
Pls guide us as how to go about designing an amplifier(low noise ) to detect a microvolts signal in series with a resistor .The design should be at 10KHz.The desig and simulation in ADS.
HI Manish,
I would recommend you to contact local Keysight Tech Support for this request
Thank you so much for this tutorial. I'm a newbie in ADS. Could you tell me how can I get the Workspace (in tab Folder View), like at 20:28?
Before watching videos in this playlist, kindly spend some time watching these: ua-cam.com/play/PL9OnCetH8TYrWFGB4QkDP8HVaY-Aum6Hc.html
You could simply right click and create any number of folders and then drag and drop designs, data display under specific folder as needed.
Thanks for your enthusiasm. I mean how can I get the Part1, Part2 and Part3 folder at Workspace (like at 20:28)? I will need to do it by myself or if you have links to download it?
I have created step by step tutorial with step clearly explained and demonstrated so that designers will be able to do it on their own by putting their own efforts...😊
@@BhargavaAnurag Thank you so much!
Awesome, Keep Inspiring us Anurag Sir.!
Appreciate your feedback...!! Enjoy the learning...
Well done! Excellent explanation. very valuable content for RF
Glad it was helpful!
Hello,
Thank you very much for this valuable tutorial. I have an S-parameter model of a transistor and not the device model. now I am wondering how to bias the model and adding transmission lines to create lambda/4 and other lumped components. as I see here, we need a bias circuit to connect to Gate and Drain nodes. while in an S2P block, I don't know how to implement this. finally, I want to generate the layout for fabrication but I don't know what is the starting point in this case ( S-parameter model)
again thank you for your hints and helps
Hi Ehsan,
Process will be exactly the same with no change at all as shown in the video. Only difference would be that your circuit performance won't change if you change the bias voltage as you have only S2P file and output power will never compress and it will keep on increasing so there is no fun in doing HB simulation. You can skip the DC IV simulation part and go directly to stability analysis using the S2P file you have. Make sure S2P does have noise data else you won't be able to see Noise Figure which is important for LNA.
You should still design the bias network and attach it to rest of your circuit. Port1 of S2P file will be gate (or Base for BJT) and Port2 will be Drain (or Collector for BJT).
@@BhargavaAnurag hello Anurag,
Thank you so much for information. I am working and studying on your design. Everything is ok so far, just i am a bit confused on the bias network cap section at the end of it where you have some pads and a capacitor parallel to it . Is it a kind of special thing ? I have seen different bias networks as chucking RF. Is there any hint or book for this area to read more and understand more to manipulate such designs ?
The video is very good and helpful. However, I would like to ask about the bias network. You mentioned earlier using 105 ohms impedance and 90 degrees. Can this method also be used for power amplifier design, or is it only applicable to LNA?
You could use similar approach for PA input bias, but you need to pay attention to output bias section as per the dc current and it may not be possible to use high impedance line due to high drain/collector current.
Hello! thanks for your work, my i askyou.. while running the same circuit in my computer i dont get any of the mu or muprime graphs... why that could be? Thanks
Hi Sergio,
I am not sure why that might happen but I know one of the ADS version had a bug for the same. If you use newer/latest ADS release, it should all work fine for you.
@@BhargavaAnurag Thanks for your time answering my question. I just found it was because i had to create the chart in the first place and then select the parameters to load in (Mu and MiPrime). Have another question if you have the time.. Im trying to design a RadioTelescope as my final project for my engineering degree, right now i cannot find the same transistor as you are using here, but limited to some NPN BJT i can find. Do you have rocomendations about the topology? or different steps to do the analisis for the LNA? Thanks again for your time. BTW using ADS 2016
@@sergioruppel7269 You can get the transistor I used in the library provided in the ADS: C:\Program Files\Keysight\ADS2016\oalibs\componentLib folder.
Copy the RF Transistor zip file in your project folder, unzip it and then add this design kit like any other library in ADS and you should be able to get ATF21170 transistor for your use. You can see how to add vendor components from this video: ua-cam.com/video/Vf6dVKLxe4M/v-deo.html
Topology using NPN BJT will also be very similar except that you will use a current source in the Base instead of a voltage source like I used for the FET device.
Hello Anurag,
Thanks for sharing this video.
A quick question, Series Resistance at the output will cause a drop in gain like you said. You still kept the 20 Ohm resistance at the output while introducing the shunt RC network. Can't we just remove the "R" at output and tune the input shunt RC network for stability?
If you can achieve stability with only shunt RC then why not. However, that may be but difficult and eventually you will need to lower shunt resistance value and you will see similar loss. Putting series resistor in output is not all that bad as long as you do proper analysis to achieve required gain that you are looking for. It all depends on the device characteristics so designer will need to play with all the possible topologies and pick the one that gives best results.
@@BhargavaAnurag Thank you Anurag for that quick response.
Really appreciate it.
Thanks a lot for this tutorial, I could not figure out how the 90deg and 50 Ohms became 1.1 width and 19.8 length. I have used LinkCalc and the result was 18.6 length and 1.07 width, ??
Kindly check the dielectric parameters carefully. If not, just proceed with what you obtained as it will not cause a major issue in your design work.
I checked the dielectric parameters carefully and test both results,
Your results was the most suitable to the case, even the linkcalc was not the same
Most of thanks,
Yes, now it is ok, I did not notice that the electric Impedance should be 105 Ohms
Is there any reason (specific reason) of choosing that value? (105)
Great Video. Sir please help me how to import the PDK file into ADS because it always shows the warning or error invalid lib path. How to remove the error or import the PDK into ADS.
Kindly see this: ua-cam.com/video/Vf6dVKLxe4M/v-deo.html
Thank SIr. How can i download this presentation? I like that!
Hi Hung,
I am glad you liked the presentation. Unfortunately, there are no slides for you to download as of now. You can pause video at every slide and take snapshot to create your own copy.
Hope this helps in some manner.
Could you please tell me at which tutorial you talk about inserting array of vias?
You mentioned in the video that you have tutorial about it
Hi Ali,
Please refer to videos 41-43 under Learn ADS in 5mins playlist to get full context of it. For via array, you simply draw 1 VIA of desired diameter/radius and then use Edit->Copy/Paste and select option of Step & Repeat to enter X & Y values etc...
Hope this helps.
@@BhargavaAnurag
Thanks for your reply It was really helpful👌👌
Hello Sir Anurag !
Hello everybody !
Need help on the following
I setup s-parameter simulation of ATF-21170, i get a warning message "Resistor A1.RSSP is shorted"
why this warning is appearing ? and how to remove it ? Commnet please
Kindly ignore the warning message, that’s normal.
@@BhargavaAnurag sir thanks a lot for quick and kind reply
Thank you for this perfect tutorial. I didn't understand a point in Step4 bias NW. There is DC_Block just after TermG1 in schematic design, but you didn:'t put the DC block just after the Termg1 in the step4. So when you feed the circuit with DC_feed from the point between the MSTEP and MLIN-TL4, wont the DC current flow throughout the MLIN TL1 to the TermG1?
Hi Sabri,
Kindly have a look again and you will get answer. There is coupling capacitor between DC bias point and the Termination both at input and output side.
@@BhargavaAnurag Thank you for your response. One more question, isn't this FET P channel?
Hello Anurag ,
Another question regarding LNA design .
How do you decide the value of choke and dc blocking capacitor for lower frequencies ?
Hi Amith,
You just need to remember that you have to isolate DC and RF in the DC bias section and the prime objective to let DC pass and block any RF energy so you pick a choke or inductor that can give you SRF around your RF as at SRF (Self Resonant Freq) it will have parallel resonance offering the best possible resistance to prevent RF leaking into the DC section, other factor includes to have low ESR to avoid DC drop etc. But some people make it part of their matching network criteria change a little bit so its subjective to what topology you want to work with.
Similarly, DC blocking Cap commonly referred as coupling capacitors in the path of RF ideally should have SRF (Series Resonant Frequency) at RF frequency to give you least resistance in the main path but then it all depends how you decide to use this as some time we use it as part of the matching network (like I did in LNA video) then you go with any value suitable for matching application to kill 2 birds with single stone. Prime objective is to block the DC which any Capacitor value will do and then whatever other purpose you may want to use it for and then come up with value accordingly.
Look for some App Note on this topic for more details, I remember there were some nice ones from MACOM, NXP etc
Hope this helps....👍
@@BhargavaAnurag thank you so much.
Thank you very much .This video is very helpful for my project.Could you please tell me the design equations
Hi Sandeep,
There is no major equations I used here but you can surely find relevant equations in book like Gonzalez etc.
Thank you, Sir for this wonderful lecture and covering the complete design strategy of LNA. Unique to this content is the stability network design. Because in most texts on LNA design, impedance matching of the active device under unconditionally stable condition is shown and not the strategies on the stability network.
Therefore, you are right when you mentioned that this material is 'not available elsewhere' in the Introduction slide😀. Do let me know if this perspective is correct.
Sincerely,
naive MMIC designer
Hi Rahul,
You picked up one of the many good points which aren't discussed in many books. Watch both of the LNA tutorials carefully and you will find many other points/topics like Stability...😊
Sir, you already told that you'll upload the full tutorial to design a broadband RF power amplifier including load pull, source pull simulation to determine optimum load & source impedance of the transistor with the use of ADS software on november. But still there is no tutorial about it. Can you please do it within few days. We are really in the nead of it because of our research project.
Probably you haven't turned on the notifications for my UA-cam channel. I already post 2 videos on PA design and will post the final one next week. Kindly check Tutorial 16 and 17 under RF Design Tutorials playlist and for future make sure notifications are switched on so that you are always notified about the new video uploads...
@@BhargavaAnurag thank you sir, sorry for inconvenience. I'm turning on the notification now.
I am doing just schematic simulation of an LNA....I do not want to do a pcb layout
Do I need to do Bias Network?🤔
@@SylvesterJuniorTettey if you want to approach it as near practical then yes otherwise just use ideal DC Feed and DC Block..🙂
@@BhargavaAnurag Thank you sir
with regards to a project I am working on and I am currently stuck,
I would like to reach out to you by mail or by any means... How do I contact you please?🙏
hellow i have some problem in first step when i show the characters of the transistor and run simulation this message appear Warning detected by hpeesofsim during netlist flattening.Resistor `A1.RSSP' is shorted.' please help me..
Hi,
You can ignore that warning and proceed.
Great Explanation! I wanted to design the LAN by "hand" with some python scripts and smith chart but did not had the whole overview after reading books and application notes. With your explanation its much clearer now.
Glad it was helpful!
Sir,you didn't mention anything about design equations you used.can you please mention them so that I can use them for designing lna for 1-3GHz
Hi Karanam,
As you can see I haven't used any equations during the design process. You need to apply fundamentals and if you want 2GHz wide BW LNA on 2 GHz center frequency that is 1 octave BW based design so might be quite difficult on a PCB and MMIC might be more suitable process for the same but again it depends on what specification you are looking for. Its all about Broadband matching network design and whether selected transistor gives you good enough parameters to design such broadband LNA. Check out Broadband Impedance Matching tutorial video to get some more understanding....
Sir,
I saw many videos all are well explained. thank you so much.
You are most welcome
Sir, after I unzip the design kit and click ok when the dialog box appears if I want to add, there are no libraries or schematic added to my workspace. What should I do?
not sure what you are doing wrong. Kindly contact your local Keysight tech support team to show the problem you are facing and they can offer solution.
sir! does microstrip line technology is easy process to do? because I'm as a engineering finale year student, doing LNA design for the 1st time...in ADS as you shown in this video. Is it achievable?
Hi Prasanna,
Microstrip is the easiest printed line process.
Whatever I showed you in the LNA design is surely achievable and I talked about all practical considerations that you need to take during the design.
EXCELLENT VIDEO TUTORIAL SIR. VERY USEFUL TUTORIAL FOR THE RESEARCHERS
Thanks and welcome
Thank you for your exellent tutorial !
Glad you like it!
Very good initiative, really appreciate your efforts in sharing your knowledge
It's my pleasure
Hello sir I want to design a 60 ghz LNA using 90 nm Mosfet.
Can you guide me from where to start?
Hi,
I don't plan a video on that any time soon but you will find some relevant info online from other people....👍
@@BhargavaAnurag I looked for online but I can't find any source that explain it from scratch like from mathematical equations to design.
Sir, how can I download these transistor kits for my ads?
Hi,
You don't need to download the kit that I mentioned in this video. All the components can be found under the ADS installation directory e.g: C:\Program Files\Keysight\ADS2021_Update2\oalibs\componentLib
If you are looking for any newer vendor transistor kits that is not available under these libraries then you could visit respective vendor's website to look for the models.
Hope this helps.....
Found that library, thx a lot, all the best!
Hi sir,
I am designing lna for 2 ghz using NXP BFU690f rf transistor. I downloaded s2p files it contains data of signal to noise ratio files and not including the signal to noise ratio files also. Which file has to used for designing.
You would need to use one with the noise parameters
Sir, Thank you for giving a wonderful lecture video. This helps very RF engineers and academicians to know LNA in detail. I am designing a Microstrip Isolator, can u help me with how to include ferrite magnetic materials in the design? Give some book references for the design.
Unfortunately, I have nothing to help you.
Excellent tutorial sir. Thankyou very much sir for the lesson. Sir i was wondering if you can help me out with 2 stage amplifier design for a mmic designer.
Hi Nishant,
I don't have bandwidth to support an actual design as a consultant but you would definitely find consultants in India and elsewhere to help you on paid basis depending upon scope of work.
Doing 2 stage or 3- stage design is not so difficult if you keep following the fundamentals and take care of interstage matching and stability of your circuit.
@Anurag Bhargava Dear Sir, I have gone through LNA tutorial 9-10 videos but it could not solve the problem. First, you used series resistance at the input and output sides separately. Then, you deactivated input resistance, and connected RC network towards the ground. The values were picked previously and there was no information for derivation. Best regards.
I showed concept of placing resistor at different places and its impact on the noise figure so don't get confused with that. In an ideal case you can place resistor on the output side for LNA and if device is not fully stabilized then shunt resistor can be used in series to capacitor (to avoid DC) but the resistor value should be as high as possible to avoid resistive loading which will degrade noise figure so its all about balancing the different parameters like gain, noise figure, stability etc
Sir, Your tutorials are very encouraging for new learners...!!
One small request, for upcoming videos, if possible please provide links in the description for previous video tutorials wherever you are mentioning it in the current tutorial..
Hi Manish,
I will try to do that, usually I always to one of the videos under "Learn ADS in 5mins" playlist for different videos for RF Design Tutorials and hopefully it is easier to figure it out based on the topic mentioned in the playlist.
congatulations for this topic, it is really helpfully, I am from latin america, could you recomend a book about this videos. with more detail because some parts i cant understand clearly.
Hi,
For normal Amplifier technology and theory, you can always refer to books like Gonzalez but those books don't talk about the practical implementation of the amplifier which I tried to cover in the video but if you want to understand the theory and concepts then those are excellent...If you have any specific query then you can post them and I can try to answer those.
Nice video... But problem here on adding the library to the workspace, it says "Error reading library definition file "C:\Users\italo\MyFirstWorkspace_wrk\MyFirstWorkspace_lib\RF_Transistors_vendor_kit\lib.defs" Library definition could not be found" What should I do?
Hi,
It seems you unarchive the transistor library inside the workspace library which is not good. Kindly unarchive it somewhere else and then add it to your workspace. This should resolve the issue for you.
@@BhargavaAnurag Sure thank you! Do you have any tutorials about including a new part on ADS (or edit), I am struggling on that? Although, I am trying to simulate the ATF34143 (I found an .zap file) and I am trying to create the matching circuit (it is possible to give me the capacitors, inductors, or resistance on the input and output?), SNR analysis, noise, gain, and some graphics... It would help me a lot! Regards!
Kindly don't mix up the things. ATF34143 model should be available inside the RF Transistor library and you should be able to place it on your schematic after including the library and proceed with your simulations by watching different tutorials I posted.
zap file which you mentioned is a old style zip format used by earlier ADS versions (but its not a component library like RF Transistor). You can unarchive the zap file by going to ADS Main Window->File->Unarchive and then browse to this file. After unarchiving you would be able to see the contents inside, it might have an alternative model representation for ATF34143 transistor and if you want then you can use the same for your simulation and impedance matching applications.
Hope it is clear....
@@BhargavaAnurag Sure is it clear now thank you for your attention Anurag! I am actually seeing you 5min tutorials and looking for my necessities (how to create a new match I/O circuit for amplifier, but still some doubts about intrinsic impedance on the point of view of source or transistor, the s-parameters and etc), I am more familiar with the Capture CIS and PSPICE for simulations. Anyway I am searching this kind of contents and appreciate yours either!
To find impedance of an active device, gain circle, noise circle etc you can watch this tutorial: ua-cam.com/video/pNSPMPPHagQ/v-deo.html
Again, be careful in your choice of words, intrinsic impedance of a device is different from input and output impedance. Intrinsic impedances, voltage or current is very dependent on the kind of model vendor provides you and may not be available in all models, I have only seen those in High Power devices meant for PA applications. They are largely used in PA designs to look at intrinsic node Voltage and Currents, Dynamic Load line etc but for impedance matching kind of application for a LNA or normal amplifier what you need is normal input and output impedance which is quite easy to find using S-Parameter simulation once you watch the above video but you need to make sure you bias level of the device is set properly and make sure right bias network is designed as all of those things will affect the impedance that you see at the input & output.
Take 1 step at a time and you should be fine, when you look at the LNA video see how we took 1 step at a time and were successful but in order to do those watch 5mins tutorials to pick up necessary skills to be employed in an actual circuit design.
Hope this helps
Hi Sir, thank you so much for these tutorial videos.
If I may, I have a question. Would you not need a T-junction component in the schematic when adding the radial stub at the time-mark 50:20? Thanks beforehand!
Yes, if you are using a radial stub in shunt then it is recommended to connect a MTEE there but it is not going to be a big problem even if you don't connect it as your RF will be largely isolated at that point.
Excellent Sir.Very well explained.This type of content is not available anywhere.
Please start tutorials, related to MMIC design also.
Sure I will...stay tuned and keep learning..!!
Loved it! Thank you!
You are so welcome!
What are the changes we need to do to circuit to make it work ah high frequency (let f=60GHz)
Hi Vinod,
For 60 GHz, you will need to design via IC process either in GaAs or Si. It can't be done using PCB technology.
Hello, this very a good tutorial. I'm designing a low noise amplifier too and it's very difficult because I usually don't use ADS software. Do you also provide services for people who want to design and simulate LNA with ADS software? Thankyou..
I don't offer such service. Which country are you based in and what specific help do you need?
Thank you Sir for the remarkable effort and exceptional content. Just one question: our frequency is 2.4 GHz and therefor lambda=124 mm and lambda/4=31 mm, your design is 100% correct but I can't understand why the quarter wavelength line's length in your design is 19.8 mm.
Divide it by sqrt(Er) to get guided wavelength…🙂
@@BhargavaAnurag THANK A LOT
I ask another question, i have to go back and forth with my design. i achived stability with my particular bias network and transistor but now my MAG is around -1.7 while it was around 20dB with the previous bias network (but unstable).. do you have a tutorial to design the network to optimize for gain with an stable system? thanks
I am not sure how gain can drop from 20dB to -1.7dB and this indicates there is some problem in the way you configured your network. Whatever I showed in this video is to stabilize device first as well as keeping an eye on the Gain as well. Kindly relook at your design and hopefully you will be able to figure out the root cause of the issue.
Sir, ATF-21170 is a NMOS or a PMOS device?
Its MESFET device and not NMOS or PMOS
@@BhargavaAnurag okay sir. Thank you ❤️❤️❤️
I cant download the workspace. Can yu provide the link for downloading the workspace?
It is available at the link provided in the video description. To download the workspace, you need to be a valid Keysight customer and create a Knowledge Center login account for yourself. Please contact your local Keysight tech support team for help.
Can you explain the Lamba/4 practically?
Also which transistor can you use 23-30 GHz design?
Hi,
I am not sure what you meant by explaining the lamda/4 practically? I showed the same in Part2 of the video in EM-Circuit excitation section. Please watch it to get more context or just use Smith Chart tool in ADS to see how lamda/4 behaves. Put Zs or Zl as 0 or 9999 and then use a transmission line and see what happens if you insert a 90deg line i.e. lamda/4.
For 23-30 GHz, I am not aware of any discrete transistors available. Best I have seen is till 18-20 GHz, www.mitsubishielectric-mesh.com/products/pdf/mgf4965bm_1211.pdf
Beyond 20GHz, your board and assembly parasitics will be too hard to contain and it is recommended to design using a suitable MMIC process.
Hope this helps in some manner...
What is a choke aproach?(min 41:00)
Not clear about your question here.
Thank you? Could you help please? You are said, that frequency is 2,4Ghz and lambda/4 line is 19.8mm? How is it possible if lamda for 2.4GHz is 0,125m? 0,125m/4=0,031m
I am not sure which formula are you using? Try this:
lambda (in mm) = 300/(freq_in_GHz*sqrt(Er)) so if you take freq as 2.4 GHz and Er=4 then the calculation will be:
Lambda (in mm) = 300/(2.4*sqrt(4)) = 62.5 mm i.e. lambda/4 = 62.5/4 = 15.625mm
Hope this clarifies...😊
@@BhargavaAnurag, yes. Thank you very much!
Hi Anurag,
I think it is important to mention that noise fiqure is strictily defined as the ratio input SNR divided by output SNR when input noise temperature is 290 K. Otherwise, great video!
Good point...refer to the video at 27:17 and you will realize that it was covered...😜
Thanks for the comment anyways and hope you enjoyed watching it....👍
Please sir, is it possible to build a network of LNA(5.5GHz) and IF amp(300MHz) together in single circuit just like the circuit you have while doing the recap of LNA( that contains antenna and mixers)? If yes, please sir how can one go about it sir? Thank you in advance.
Very useful video again from you. Thank you so much for those practical tips. One comment: I felt that you could have explained DC bias network creation more in detail :)
Thanks for your comments. What else would you liked to see in Bias Network creation?
@@BhargavaAnurag Appreciate your tutorial. These are questions I had:
1. For i/p, o/p microstrip in bias n/w, you mentioned 1-2mm length with 50Ω would be fine. So that will give around 40deg phase shift to input signal based on line calc result. Is that okay ?
2. You were saying 105Ω would be fine for lambda/4 line. I understand it wouldnt get too hot as FET will be drawing less current. But how would you know what is optimum impedance and how hot this microstrip would get ? Is it to be verified with 3D simulation ?
3. Doesn't Mstep add any electrical length to lamda/4 line before it ?
@@satyat7051 Here are my comments to your queries:
1. There is no concern if these sections provide 40deg or whatever phase shift as we can always do the matching network according. Also, 1-2mm is a typical/general guidance and you need to know your own fab requirements to make sure components can be soldered, leads can be mounted etc.
2. More impedance the better to block the RF frequencies. There is no special need of 3D simulation, you just need to compute current carrying capacity of a Microstrip line as per the width and these formulas are there in any Microstrip text books like T.C. Edwards etc.
3. Mstep is only to account for discontinuity effect due to different widths at the junction and has an insignificant contribution to electrical length.
Anurag Bhargava thank you for clarification. I will refer to the text book that you mentioned. I am interested to relate temp Vs current on microstrip line. . Again, Your tutorial is amazing :) I hope to see PA design also from you.
Oh my god I am so thankful, you can't even imagine Sir, this video answered me a lot of questions.
I am glad that it was of help to you...Keep learning...👍
Can I import BFP740FESD FET transistor in ADS,I am unable to that.
It seems to be a low noise transistor for LNA applications. If so, you don't need a full non-linear model and you can design LNA by just having S2P file with noise parameter data that transistor vendor can provide to you or it might be available on their website
This is such a well organized video. Like you rightly said, text books are so voluminous that reading the details we can't easily get the design concept. I hope you continue making such videos for the benefit of the community. Hats off.
Just one question. If I decide use a FET on a CMOS process, will the same specifications (NF, Gain) that you've showed here provided in the PDK?
Loved your comment...!! Thanks for providing your feedback.
For CMOS, you will have MOSFETs instead of FETs and NF will not be as good as what you see here because Silicon is a poor quality i.e. Noisy substrate for LNA and that is why mostly you will use Low Noise GaAs pHEMT process for LNA designs. Using CMOS PDK transistor models you can always find out the NFmin, Gain etc as shown in the video for sure...
Silicon is quite a cheap & abundantly available material compared to GaAs plus you can have RF & Digital circuits on a single chip to design a complete SOC (System on Chip) for a Transceiver system.
In practical systems such as Mobile Phones, you always have RF Front end module (known as RFFE modules) where PAs and LNAs are designed with GaAs processes, Switches using SOI and tons of SAW and BAW kind of filters for various bands etc) followed by Silicon-based Transceivers or Modems. Each technology has its pros & cons as you select the implementation based on the specification & size constraints on hand...!!
Hope this helps in some manner....
@@BhargavaAnurag Thank you very much for a detailed and insightful response. I was curious of the question because I did my PhD on process engineering applied to LNAs on PD-SOI substrate. And because of specially engineered Trap-Rich SOI substrate, substrate effects can be significantly reduced compared to CMOS. From what I understand, heterogeneous integration is what is preferred for RF frontends incorporating different technologies.
Also, what is your opinion about future of SOI? In my literature review, I found some examples of devices which I thought had really good noise performance. How does it compare to GaAs pHEMT?
ieeexplore.ieee.org/abstract/document/7874382/
ieeexplore.ieee.org/abstract/document/8439132/
Hi Arun,
Thanks for pointing me to these references. I don't have much experience with these new processes as of now and looking at the current trends followed by major companies I can tell you III-V is still the preferred choice for LNA as well as PA and SOI is very popular for Switches in the RF Front End modules.
But again its always good to be in know of the newer & upcoming technologies.
@@arunbrvce Super observation. Thanks for sharing.
Outstanding Job.
Thank you! Cheers!
Hello , I want to design with BFP196W for my assignment , can you help me ? Thank you
@@duckhiembui4480 you should do it yourself by learning from this video
Sir, Thank you very much...
Can you please make a video on power divider.(n way splitter)
What do mean by n way splitter? can you be little more specific?
@@BhargavaAnurag sir 2,4,8,16...way power divider
Got it...will try to cover in future tutorials...!!
Sir.. can You provide the link for AFT21170 PDK non linear model download ?
Its already included in the ADS library. Watch video carefully again on how to add this library in your workspace else this video 9 & 10 will help you as well: ua-cam.com/play/PL9OnCetH8TYrWFGB4QkDP8HVaY-Aum6Hc.html
Sir I am quite new to RF design and trying to design for my university project. So this is my question.
1. i am designing push pull class B amplifier in frequency of 1GhZ below. Is it necessary for me to create Bias network design to replace the dc and rf choke ?
2. If it is not necessary, how to know the right value for capacitor and inductor to put in my dc block and rf choke? Any formula?
3. For the Tlines that connecting to each devices, what is the rule of thumb (range) for choosing the length and width of each T line.
I mean MLIN not Tlines :)
Hi,
For freq below 1GHz, you don't need to use MLINs for bias network as you will easily find chokes/inductors for RF blocking purposes. Kindly google for app notes from vendors like NXP and you will find good papers on the same.
Can anyone suggest me a good book for LNA design?
hi sir....tutorials are very useful....i have doubt sir,....How to convert lumped element to microstrip.. inductor converted to microstrip and same as capacitor....
Hi Udaya,
There is no direct method as such but you could use Reverse Engg method as explained in video 21 under Learn ADS in 5mins playlist
Hi sir, its wonderful lecture with excellent pronunciation...
You have used pf_hp_ATF21170_19931015 GaAs model transistor to design the LNA...
Can you tell us which model is best for GaN based LNA..?
Thanks,
Naresh...
Hi Naresh,
I don't think there is anything called GaN LNA as GaN is known for high power application and not for low noise. For LNA, GaAs HEMT is still one of the best technology to use. ATF21170 that I used is a pretty old device, now a days there are much better low noise HEMT technologies available.
Sir, my work is based on GaN HEMT device to design an LNA. But, searching lot to select a model for GaN...
So, asked you for help. Thanks anyway for prompt response...
If you know model for GaN, please let me know...
@@BhargavaAnurag
Sir, my work is related to GaN HEMT device to design an LNA...please let me know if any model you'll come to know..
@@souparnika6931 I would seriously advice you against pursuing this work & I am not sure who gave you this work? Due to the reasons I mentioned before GaN is a high power process and it provides high bandgap devices for high power application and noise is the least concern when you deal with those devices but if you are lucky to find a GaN device whose NFmin is < 1/2 of your target LNA circuit noise figure then ofcourse you can go ahead and design LNA.
Sir ,I have one concern ,at mmW frequency ,what type of resistor should be used for providing stability of the device..can be use thin film resistor or simple resister of 15 ohm..?
both should work. Resistors usually are not frequency dependent but be careful in not sucking up too much of gain/power while using them.
I have seen some thin film resistor in TLine microstrip pallete..there is given some equation...RS( freq)=Rs√freq..how to use that equation at higher frequency??. according to that equation sheet resistance may vary at higher frequency...I don't think show ..it may not give a good agreement between simulation and measurement results..
Hi Saurabh,
For thin film at such high frequency, I wouldn't recommend to use schematic model. You should define the correct stackup with correct material properties in layout and then create a parametric EM component for yourself to be used in your design.
Thanks a lot sir for the guidance..
You have really helped me a lot with this tutorial. Sir, I need a tutorial on how to plot the stability factor versus capacitance or resistance
Hi Mawuli,
You don't need a tutorial video for this. Here are the simple steps:
1. Define a variable on schematic e.g. myCap = 1
2. Assign the variable to the capacitor component on schematic which then might look like: C=myCap pF
3. Setup and run the parameter sweep
4. Insert the graph and select StabFact and click on "Add Vs" and then select myCap from the available options
5. Now you will have the plot of K vs. myCap as you need.
Hope this helps
@@BhargavaAnurag Got it!! Great, in fact, I don't know how much I should thank you but I believe you shall surely reap the fruits of your kindness in the land of the living!
Hello sir.
I need to design a broadband LNA that covers 1-6GHz frequency as I am replicating a competition paper where they had used TGA2602 SM (Qorvo) transistor in cascade (the concept was consume more dc to achieve broadband performance) but transistor ADS deign kit and its equivalent model is not given by Qorvo and S2p file contains data without Noise data. We discussed about that in comment section as well.
So, I need to go for replacement transistor. Can your please suggest me a replacement transistor that can be used for broadband LNA design and also its ADS model will available by vendor's.
The design specs are:
broadband LNA (1 to 6 GHz), Gain: 13dB, Noise Figure
Hi Adnan,
You should be able to find suitable transistor from other vendors or from Qorvo themselves and you can always request them to give S2P file with Noise data. You need to do literature search and look for devices from Infineon etc
@@BhargavaAnurag Yes sir I have found an RF BJT transistor from Infineon and few from other vendors as well and their design kits are also available on ADS.
Can you please guide me if I want to achieve a broadband bandwidth of more than 3 GHz for an LNA what approach should I adopt. Please guide me in context for achieving broad bandwidth
If you are using S2P file for the transistor, you don't need to bias the gate voltage right?
You don't need to bias anything in that case but you still got to design the bias network in schematic and layout to make sure there is nothing wrong with the overall design and impact on the RF performance.
@@BhargavaAnurag Thanks so much.
Watching your videos systematically.
I have another question: Do you apply both gate voltage and drain voltage or just the drain with S2P?
@@mfonuko7420 you don't apply any voltage if you are using S2P file as file is already extracted for a fixed Gate and Drain bias/voltage
Anurag Bhargava Wow
Thank you so much. I’m learning a lot from you.
Thank you.
Excellent sir.please sir start also EMPro and Genesys tutorials as well. Thank you
Sure I will
how to calculate the SNR ?
SNR can't be simulation in S-Parameter directly as such. You don't need it for LNA as you can directly see Noise Figure which is what you care about. SNR is usually seen on Modulated Signal level....
Sir can I please get to know what is the name of the template you use for s parameter simulation
Its a simple S-Parameter template available in the list.
Thank you so much sir
Now sir could you please let me know that from where did you get the bias network template
@@nileshvatwani2584 There is no template, I created it for the bias network.
@@BhargavaAnurag Thank you so much sir... actually I was having the internship under DST-SERB-ECRA at NIT WARANGAL...so there I have to design a LNA of gain 30db
Great video as always Anurag, thanks for helping so many people in this interesting topic.
Can you comment on (or give references to) why the shunt/series impedance improves the stability of the device?
Hi Miguel,
Thanks for your kind comment. For understanding how resistors improve the stability, you can refer to causes of Oscillations in a transistor & find out how to do oscillator designs and do exactly the reverse in amplifiers to prevent that a.ka. break the loop gain chain which might induce positive feedback....😊
In simple words, while designing amplifiers we need to dampen or kill the oscillations caused due to L & Cs and resistors are the perfect components to do that. Different devices work differently hence we need to try different values or topologies to achieve our goal.
For more details, refer to this: www.mwrf.com/technologies/components/article/21846567/ensure-stability-in-amplifier-designs
@@BhargavaAnurag Thanks! Now it's clear
Sir plz cover some more topics..like filter design attenuator,IF amplifier
Sure 👍
Sir, can I get the license of ADS for myself ? Without involving institute ? As most of the content on Keysight website get restricted when I select my country.
You can always apply for the 30-days evaluation license on the ADS webpage.
hi,
how can i get and import TSMC 180nm PDK in ADS
Hi,
You can contact TSMC to get PDK for ADS. There is nothing to import here
@@BhargavaAnurag thank you so much for your answer
Sir which topology we are using here?
What do you mean by which topology?
@@BhargavaAnurag cs degenerative source inductor...like this sir
sir how can i do the same at operating frequency 4GHz
Same concept and simply change the calculation & optimization freq band to your required frequency.