TERNARY NAND with AVG Power and Delay in Cadence.

[@srinivassrinii]

how do we do DC analysis for CNTFET of Ternary NAND Gate

[@dr.hariprasadnaikbhattu]

Hi, process for dc analysis of cmos or cntfet is same. Use the link
ua-cam.com/video/TMTUmI3w9cs/v-deo.html

[@byreddyvenkateswarareddy8573]

Hi @Hari,
Can you do one more section for who are newly entry for ckt design
Can you make a digital design and analog design
Tq for your efforts tq tq

[@dr.hariprasadnaikbhattu]

Hi, I have designed for analog and digital. For any reference go through the videos.