BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 3)

[@arkyaaditya6797]

In 8:51 the same clock is connected to both flip flops, so both take value for 'a' in the same edge, which is not the thing for blocking statements? How do we justify this?

[@shivajeetiwari3816]

what is difference between ex-6.(a) and ex-2 ?? Why synthesis tool will do optimization in different way ,basically in such cases, how many Flip-Flop should be generated ??

[@yukthiprasad3383]

Might be because:
In ex-2 : Might be q2 and q1 both defined as output.
In ex-6a : only E is defined as output.

[@Locomotivesofindia939]

At 15:00
q1=a;
#5 q2=q1;
Is it possible making like this by introducing time delay at q2 assignment ?

[@abhijeetchauhan4111]

?@4.59, the code with non blocking, when I simulate, simulation time is not advancing ?

[@Tanaypasumarthi]

6:34
In non blocking condition what will be the result when time delays are different

[@arghya.7098]

all the data assignment will take place after their respective time delay.
for example,
x

[@UdayKumar-bm1el]

in example 1 what happens if delay is 6 units instead of 5 in second assignment statement

[@ashishpapreja3756]

a

[@UdayKumar-bm1el]

@@ashishpapreja3756 will c be assigned old value of a or new value of a (i.e. b)?

[@ashishpapreja3756]

@@UdayKumar-bm1el old value

[@rddinesh4]

@@ashishpapreja3756 @9:00 how the synthesizer understands that it should generate a d flip flop for the given code?

[@emmanuelinnocent4505]

@@rddinesh4 I think when edge sensitive event control (e.g posedge) is declared in an always sensitivity list, a flip flop is inferred.

[@bakeronews1]

You shouldn't change the order of E D C B A....

[@tee-nw5vx]

why

[@mrpossible5696]

0:00