Copper Pour Clearance | PCB Routing
Вставка
- Опубліковано 11 чер 2024
- When is your copper pour too close to your traces? And is manufacturability the only way to answer this question? Zach Peterson opts instead to examine this question from a signal integrity and impedance perspective.
0:00 Intro
1:05 Manufacturability
1:55 Capacitance and Impedance
5:58 The 3W Rule (is overly conservative)
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Thanks Zach! You just perfectly answered my questions when doing RF design.
Thanks Zach - very useful video and links. Maybe next time also cover creating a rule to automatically set the clearance on copper pours?
Great suggestion!
Essential concept to be considered while designing antenna feed line ...also I heard about a simple rule, that the spacing should be more than or equal to the dielectric thickness
Super helpful. Particularly appropriate you chose 50 Ohm stripline - probably the most common impedance employed. I've typically used 2X clearance for 50 ohm traces while targeting thinner dielectric to reduce trace width. I came back here for a little schoolin after my fab vendor (that has the advanced tools) was suggesting 0.914X and I was doubtful they had factored in the coplaner parasitic capacitance.
They are also suggesting a change in stackup construction. For my 6 layer PCB I had specified a 3 core stackup and they are suggesting a 2 core construction with prepreg + foil on the outer layers. I'm concerned about any variations in impedance across the 30mm long trace due variations in thickness and prepreg Dk (maybe I worry too much :)). Also I wonder about the mechanical properties of this different stackdup considering my 'works anywhere on the planet outdoors environmental constraint (albeit inside an IP65 enclosure)
Any insights are appreciated :)
For the stackup change with prepreg on outer layers, I think what matters here is the pressout thickness variation and the hygroscopicity of the material. Controlled impedance testing up to a reasonably high bandwidth should be good enough for addressing the impedance deviation. About the hygroscopicity, as long as it can be proven that there is no appreciable performance difference due to moisture uptake in core vs. prepreg then you should not have a problem. Maybe could also try a conformal coating?
wow, actual great video. loving these altium academy videos. please keep them up. - - lets see some more in depth PDN analyzer videos please. -- teach me an easy video on how to simulate PCB thermal impedance from 1 side of the PCB to the other, a C/W.
I can't believe I let this go onto the back burner but maybe we can do this with our simple voltage regulator project before we put it into Altimade
I accidentally had a pour clearance rule set too small (1W) to a USB pair, and I was both surprised and relieved to find out from the field solver that the impact wasn't that significant. My worst-case minimum differential impedance for the USB pair was still about 7 ohms above the USB2.0 spec minimum. It was a phew moment because I only discovered the mistake after the boards were fabbed. 😅
If the ground on the next layer is very close to the trace then you will be okay, I have occasional debates about this with EMC consultants and they start to realize the value of making the outer layer laminates very thin.
Hi Zach,
The videos are very useful and informative. Can you make a video giving a overview of different datasheets and the key things have to be focused on these datasheets and the standards have to be followed while implementing those technical details while designing the PCB...
Thanks In Advance :) .
Sure, sounds like a good idea... I'll brainstorm something and we will work on it
Hello,
Thank you for these amazing series of videos.
I would like to ask about when we need to put ground pour near traces and when we don't do it?
I see many designs where some put ground pour all over the pcb and some designs just don't put any ground pour there.
I heard that when you put it, it works as a shield for cross talk between traces. Also it's much easier to construct the pcb with the ground pour rather than not because pcb manufacturer need to remove it when producing which is an extra step. So what are the negative part of it?
Thank you.
Hi Fedi,
That's a great question. We actually just filmed a video about this and we'll be posting that soon. Thanks for watching and stay tuned!
Just to follow up, the use of copper pour is usually not necessary, although most of the time if you set your design rules correctly, you might not create a new problem with crosstalk or EMI, particularly if you use close via spacing. The negative part of it is that thin sections of copper pour between traces can increase crosstalk and EMI. If they don't have small enough spacing for stitching vias, then you can create a resonant cavity that allows strong crosstalk between two traces.
I would say probably don't use copper pour all over the PCB if you're not sure if you need it. Smaller sections of targeted copper pour are probably okay in specific situations, like as part of RF circuit design or if you need to suppress specific radiated EMI problems from specific components. Most of the time, if you have a radiated EMI problem in your board, it is probably caused by something else that is more important (stackup, routing, etc.) and covering the entire surface layers with copper pour won't solve the problem.
I'm not a manufacturer but I don't think they need to use an extra step to remove extra copper, I believe they just mask and etch like normal in a single step since they are using a single stencil for everything.
What if my copper pour is not GND but lets say 5V? does something change? so the set up woudl be a 4 layer PCB, Top and Bottom woudl be SGN/PWR and mid1 and mid2 GND
I think this is easiest to understand by thinking about return currents. The displacement current that is induced in the nearby copper pour depends on the change in the voltage difference between the signal line and the copper pour. The only difference in the case of copper pour at 5V instead of GND is how the displacement current equalizes the voltage drop on the rising or falling edge of the signal. Normally, when the pour is GND and the signal rises high, the displacement current flows into the GND return and negative charge equalizes the signal potential with respect to the GND pour and the plane. When the pour is at PWR, the same return current effect happens on the falling edge of the signal rather than the rising edge because the falling edge is when the potential difference between the signal and PWR is increasing. Because the plane is GND in both cases, the displacement current flow mentioned above will occur on the rising edge in both cases because that is when the potential difference between the trace and the GND plane is increasing.
How to add two different copper pour Clarence in a single design? For example, two different clearance for controlled and uncontrolled impedance traces.
Hi ElectroRoomi,
Thanks for watching, you can do this by assigning design rules to different nets or net groups. I'll have someone from Altium do a tutorial on this so you can see how it's done. Thanks again!
s=3W. Y? it should be more than 4H than it is very loose coplanar line. But yep u should simulate to double check
I bring that up because that's the way I've seen this rule listed.
But for controlled impedance lines, they will have impedance determined by a specific W/H ratio, so yeah you can convert the 3W condition into an H condition if you want....
Then you would only have approxiamtely s = 2W for 50 Ohm microstrips on Dk = 4 laminates. But yes both are loose coplanar lines. That still works as long as H is small though, you can still route into and out of the copper pour without needing to modify the trace width.
moreover there is a danger of puncture or leak for power circuits.
If you show these clearance in Gerber it will be better.
Why would it be better? The clearance you place in the PCB layout will get mirrored into the Gerber.
Can you share your what'sapp number .
We have altium software
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