Arty S7-25 Microblaze SREC SPI Bootloader featuring Xilinx Vivado/Vitis 2022.1

Tutorial on creating a Xilinx Microblaze SREC SPI Flash bootloader application in Vitis. The bootloader reads an SREC file containing the primary application from SPI flash, loads it into external SDRAM, and executes it. Running from SDRAM instead of BRAM allows for a much larger application. Give this a like if you can get your Microblaze project to boot from QSPI and execute from SDRAM.

[@1973penel]

Hi
In the instruction "updatemem" how did you know what to set in "-proc"? And the proper location ... great video by the way

[@emcalnan]

It's painful to get the instance name of the MicroBlaze in the block design. Dig through the Hierarchy view in the Vivado Source pane. I keep the name the same in all designs to simplify life a bit.

[@jberr10]

Hi
I am working on a design where I plan to use microblaze in a board with no external memory (DDR or SRAM). From my understanding, if the application is small enough ( < 128 KB) a microblaze application can be run using the FPGA's Block RAM. I am using Vivado/Vitis 2023.1, do you think that you could do a tutorial for that or give me suggestions? I tried different tutorials but they used older version of the tools and it doesnt seem to work.
Thanks

[@emcalnan]

Just put another video up based on what you requested. MicroBlaze with 128K of internal RAM. Booting from QSPI on the Arty S7-25 board. Try me at [e-mail] if you think I can still help.

[@alexsagi3937]

Hello, thanks for this tutorial, helped me a lot. Still got a few questions, I wonder if I can contact you somehow

[@emcalnan]

Threw this up there and forgot about it. Try me at [e-mail] if you think I can still help.