Xilinx 7Series DDR3L SDRAM in one IO bank - Part 1

This tutorial explains the tricks used to implement a DDR3L interface on a single IO bank of a Xilinx 7Series FPGA. It is based on the Digilent Arty A7 board but applies to any 7Series implementation.
The Vivado side of the project is covered is this part of the tuturial.
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