PCB Design Final Touches (Tips & Checklist) - Phil's Lab
Вставка
- Опубліковано 15 чер 2024
- Tips when finishing up a PCB design before manufacturing (polygon pours, solder mask, silkscreen, teardrops, etc.). PCBs by PCBWay www.pcbway.com
[SUPPORT]
Hardware design courses: phils-lab-shop.fedevel.education
Course content: www.phils-lab.net/courses
Patreon: / phils94
Free trial of Altium Designer: www.altium.com/yt/philslab
Free search engine for the best quality components from Octopart: octopart.com/
Learn about Altium 365, the electronics product design platform that unites PCB design, MCAD, data management, and teamwork: www.altium.com/altium-365
[GIT]
www.github.com/pms67
[SOCIAL]
Instagram: / philslabyt
[LINKS]
Stitching Vias: resources.altium.com/p/everyt...
Fiducials: resources.altium.com/p/are-fi...
[TIMESTAMPS]
00:00 Introduction
01:50 PCBWay
02:34 Altium Designer Free Trial
03:24 Board Overview
04:57 #1 Schematic & PCB Synchronisation
05:30 #2 Polygon Pour Clearance
06:43 #3 Thermal/Copper Balance
07:10 #4 Stitching
07:57 #5 Polygon Pour Clean-Up
09:12 #6 Plane Voiding
10:59 #7 Non-Functional Pads
12:52 #8 Teardrops
14:48 #9 Transfer Vias
17:02 #10 Missing Plating
18:08 #11 Fiducial Markers
20:14 #12 Silkscreen
22:38 #13 Solder Mask
26:59 #14 Mechanical Checks
28:40 #15 Polygon Repours & Pour Order
29:51 #16 Design Rules & Routing Completion
31:49 #17 Gerber Viewer
33:40 #18 Footprint Checks
36:37 #19 Manufacturing/Assembly Info
37:45 Outro - Наука та технологія
Thanks for watching! What final touches do you add to your boards?
In a future video, we'll cover a full PCB design checklist and make that a 'collaborative' GitHub repo.
I only used KiCAD (just a lone, retired old fart) and I rely on the software to see if I've cocked anything up. I recently failed to do that as I moved from 7.x to 8.x because I got caught up with the production delivery (normally done automatically by an extension).
So I took my eye off the ball and planted a pressure-relief hole (air pressure) right through one of the supply lines. My board house spotted it and sent me an email.
That would have been pretty expensive in relative terms, both in price and lost time.
What I do is do not open the design for a week or two if possible so when you see it after a longer time you can see all the stuff you haven't seen before
Hi Phil, how are you? I am sure things are quite busy. Is the video on "5 Jellybean SMPS IC" still on the list of TODO things?
And again and again i can see a video with rich amount of contents and notes from phill.
For the people that are new here this is a golden hints that u cannot find it for free.
Thanks again phill for this amazing video.
Idk why but im waiting for more professional advance digital hardware course because you teach me well😊❤
Thank you very much for your kind comment, Patrick! Many more videos to come :)
Phil's Lab drinking game. Have a sip each time Phil says "so to speak".
yeah, but I'm going to stay sober, because I don't want to miss any of Phil's speaking!
Best 38 min on UA-cam, Thank you, Phil! ❤
Thank you very much :)
Excellent design review! My first PCB layout was in 1980. Back then we used 4X light tables, vellum and decals. (Much light masking tape)
A photographic camera, the size of an industrial CNC machine, was used to reduce the taped layout to 1:1.
Around 1985 I did testing as part of a design team that developed a PCB layout program called Electronic Tape (ET).
What a relief from the tedium of manual layout!
My my. We have come a long long way!
Thanks for helping others clear the way to good layout.
Thank you very much! Would've been cool to be part of that process for sure - but in a way I'm glad we have fairly accessible ECAD tools and PCBA houses these days haha..
@@PhilsLab Yeah... no! I started on PCB layout in 1979 as a summer job... and since the outfit I was working at was a barely funded startup, I got to work on taped layouts at 1X, using tapes as small as 1/64" (0.4mm). Not very fun. However, being part of the process of _escaping_ from taped layouts would definitely have been exciting! Those olden days experiences tended to fuel considerable patience with the early clunky DOS-based software, and modern tools are fountains of happiness 🙂.
That A-scope looks AWESOME!!!!
Thank you!
I always put a rectangle of silkscreen somewhere for later marking with a sharpie to show when boards are tested/programmed, or just a board number.
that eurocircuits tool sounds very good. I will give it a try. Thanks
YES! Been waiting for a comprehensive list from the man for a while.
Thanks, Mark! There'll be a full PCB design checklist vid/repo coming out as well.
Hi Phil, thanks for the content.
Altium has a general return path design rule check in the Highspeed section which is pretty handy.
Altium is doing their advertising really well, curious how many viewers can actually afford it..
Hey Phil, nice to see that my workflow here is pretty similar to urs before finishing a board, but u gave me some extra points to watch on👍🏻
Thanks, glad to hear we have a similar approach :)
I wish Phil would collab with Robert Feranec on something, the thing I like about these two people is the importance of being as prefect with the PCB design process as possible. Lots of pride in the end product.
Thank you! That's definitely something I'd love to do in the near future - Robert and I have actually been chatting about that in the past.
Good amount of useful tips. Thanks for sharing!
Thank you, Adam!
Wanna see design walkthroughs for HDMI for designing control boards for displays next 😁😁
13:57 I think you should check the "Force Teardrops" to make sure everything has it. In the past I have had it miss ones that would violate DRC and not tell me about it.
09:00 - Side Note 1 - Also poured areas that are only stitched with a single via should either get an extra stitching via (and if larger island) with some seperation to the original via, or just be removed. Otherwise the lonely stitching via functions as a antenna feed for the poured EMC patch antenna 😛
09:11 - Side Note 2 - Not mentioned but visible in the upper middle left: peninsular pours like the gray area between the two purple lines should have at least one stitching via near the furthest point away from the "main land" (better some more) as can be seen here, or removed (like the example at 08:55)
Some great tips and reminders in there, thanks! although I do find it hard to put the 'Brush' down because I keep tarting it up and shifting stuff around and at times have had to pull myself and say "It's done damn it !! " send it off......cheers!
Thanks, Andy - definitely, I could continue tweaking the PCB for a very long time as well...
TIL the trick of removing the unused annular rings on vias. I didn't know you could do that!
Thank you for much! I took notes of this video... As for tip#3 copper/thermal balance - it's difficult for me - i've conflict - thermal balance and situation for example when power pcb trace should go through all pad of capacitor, for improving EMC...
Yes, there's always a compromise and it does depend on the situation!
Every time I look at a design by Phil I feel really bad about my own designs :D
Oh no haha, you shouldn't!
@@PhilsLab Well.. it did help me big time when laying out and routing my boards. I feel that learned a lot, going from no experience to being able to do what I do now. So saying that is a big compliment!
24:58 and subsequent: Quite a bit of discussion about "bridges". In my view, "bridge" should refer to solder creating an unwanted bridge from one pad to an adjacent one, and Phil does use the word in that manner. However Phil uses the word bridge to also refer to the sliver of solder mask that helps to _avoid_ solder bridges. I think this is confusing. Better to call these something like anti-bridge solder mask slivers, or something like that. No need to add to the confusion already precipitated by the "solder mask" layer actually specifying where _not_ to place the solder mask 🙂.
Please release videos on designing a flight controller for quads with video telemetry project with ir sensors for obstacle avoidance.
Actually recently got myself a micro quadcopter frame that I plan on making a simple FCS for :)
@@PhilsLab Yes please, your old fc design isn't really practical for quads that much. It'd be nice to see an up-to-date revision with compact size factor that's more inline with current trend
@@PhilsLabSounds good. Not to make 'demands' but if you looked at ESC design and made it an all-in-one board that would be good.
ELRS receivers are completely open source so you could integrate that as well possibly (its super simple, MCU ESP8285SX1280antenna
Yes please... Make this tutorial thanks
I also give myself a week or few after I finish a board and before I order to manufacture it. I use this time to check a design periodically. Sometimes I ask myself: "how a h.. you could make such st.. thing" after some additional check.
Yeah, I do the same - definitely needed after staring at a design for so long!
I usually give myself a week to think about all the things I forgot... that's the week while the PCB design is already submitted to Chinese PCB house and then getting shipped back to me 😞. Seriously though, avoiding such regrets motivates thorough checklists!
Great Videos! Could you make a video explaining the purpose of the exposed copper on the pcb edges and vias within it as well as how to generate that in Altium? For a circular shaped pcb or a hexagonal pcb?
Also, A video with a hexagonal pcb and its routing is very much needed. As the angles in a hexagon arent 45 or 90 and in altium, routing is fixed to 45/90
Thank you! Possibly in a future video, yes - thanks for your suggestions.
amazing video go ahead
Great video
Thanks, Lucas!
@@PhilsLab The website for checking footprints its an absolute 10/10. Thank you for this information. Wrong footprints is one of my most common mistakes. Let's see if i can reduce the "error rate" with this tool. Thanks again. Have a nice day.
Glad you found it helpful - definitely been a good safety net in the past!
Just THANK YOU!
Thanks for watching! :)
Excellent material!!! Any infos about the A-SCOPE? :D :D :D
Thank you! Having it manufactured at the moment - it'll be similar to a QA403 but Zynq-based, with Ethernet as well.
Phil, how are you? In some of your videos I see you explaining about decoupling capacitor and showing that it is necessary to apply 2 GND vias as close as possible to the capacitors. Before I only used 1 via. It's wrong? Why do you recommend using 2-vias GND?
Hey, minimum I would suggest is one via per pad (if using planes). Placement and number of vias can reduce inductance and improve decoupling however in certain situations.
@@PhilsLab Thank you!
In regards to removing unused pads; is there any reliability concerns here regarding the platting in the barrel? I know its common to remove them in HDI designs but during the fab process there is usually a step called 'etch back' that exposes the inner layer copper to the barrel to allow the platting to grab onto the inner layers. With the inner layer pads removed could there be a risk that during thermal cycling that the vias are weaker?
I spoke to some manufacturers about this and they didn't suggest any reliability concerns.
Phil -- regarding removal of unused pads on vias: What do PCB manufacturers think about this? I don't know exactly how through-hole plating works, but I would have thought that it might depend on having pads (annular rings) at beginning and end of the plated barrel, no? I certainly see that PCB houses list a minimum annular ring width. But perhaps that's necessary only if a trace connects to the hole?
Hi Graham, I actually spoke to some manufacturers about this and apparently it isn't an issue. I do leave the start/end layer pads though, although that isn't strictly necessary.
@@PhilsLab Thanks, that's useful information.
About Non-functional Pads: Does it only remove the annular ring from VIA in all layers except the first and last layer?
I'm asking because VIAs are galvanised in the last production step and it might not hold in place, if the annular ring is missing on both those layers right?
Yes, by default it'll keep outer layer pads.
Do I need tranfser VIAs for differential pairs too? How would you place the VIAs then?
Yes - I either place one symmetrically and equidistantly to the diff pair vias, or one transfer via per diff pair via either side.
Hey, I've noticed you switched ON your component designators :)
For prototypes, if there is the space I'll add them :)
Are these cross fiducials a library? or all handmade. I tried to create them in KiCad 8 but i failed...
These are custom made - I would suggest staying with round fiducials however for the most part.
as a smt machine operator i have to tell u its pain in the ass to deal with cross fiducials, becouse it so reare wee have to manualy change type off fiducials, why not stick to things that just work, much love
also the red soldermask is the worse to use, becouse on AOI sometimes itss not working 100% perfectly
Thanks for the info! I spoke to some manufacturers about these fiducials and they didn't bring up that point.
Hi Phil, I sent you an email from contact form on your website. Is there other way to contact you? I didnt get reply this far.
Hi sir❤️🎉🎉🔥🔥
Hello :)
👍🙏❤️
4 minutes delay, sorry for that.
No worries :D
Why do you include the layer views in your fab drawing? I find it to be really silly- its not usable for anything. Its not useful for debug. I see lots of engineers include it- so there must be a good reason for it, but for the life of me, that reason is lost on me.
You're right, it's not particularly useful - but it can be a small sanity check of layer ordering when manually comparing to Gerber/fab exports.
Well surprisingly the inner layer views CAN be useful. Not long ago, I had a 3rd party module that had some jumper tracks that you could cut to set an option. Unanticipated by the designer, the cut location of the jumper was right above another vital trace on the second layer. So if you cut the option jumper slightly too vigorously, you would cut the 2nd-layer trace and the board would no longer boot. Having the internal copper layer view available allowed figuring out what net was cut, and how to patch around it. We learned we were not the only customers who encountered this issue.
@@Graham_Wideman ^ this. I've also had similar situation where default jumpers need to be cut for debug/DV/testing and have had issues with inner layers shorting out. Also don't forget that some very expensive boards will be repaired or have modifications made to the inner layers, the outer layers will be ground away to access the inner layers and then epoxy added, not uncommon at all, IPC covers it in various standards.