free KiCad trace impedance simulation via TDR method (trace impedance over distance) using openEMS
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- Опубліковано 30 вер 2024
- Tutorial on how to install openEMS:
• free KiCad Wave Propag...
Link to the KiCad layout:
drive.google.c...
Link to the most recent "FreeCAD to openEMS" github page:
github.com/Lub...
All tools for this video are completely free (even for commercial use):
KiCad
openEMS
FreeCad
This is awesome, you make the barrier much lower to make simulations with Kicad!
Happy to hear that! :)
Great tutorial, but in this particular example you get those giant reflections on a straight trace only because of the copper plating on the top side of the PCB (all around the trace). This creates parasitic parallel-plate line which allows the reflections to propagate and reflect off the boundaries. If you delete this top plating layer you will see a much cleaner picture and the influence of the PCB edges will be negligible.
Yes, removing the top copper would turn the trace into a microstrip line, which would reduce reflections but increase overall emissions, as microstrip lines radiate more than coplanar waveguides. Adding via stitching is a good enhancement, though using a stripline by embedding the trace within the PCB would offer an even better solution.
@@panire3 I see. Thanks for the clarification!
Uploaded just 29 Min Ago, i am glad i found This channel for simulating my Kicad Boards since i struggled at the beginning to use OpenEms.
will there be any Thermal Simulation in the near Future ( it is so usefull in low Voltage high Power Applications)
thank you Panire.
sadly thermal simulations are the only thing that i have placed behind a paywall on the plattform udemy for about 13USD if you have a coupon. If you are on a budget, you will even be able to find a hidden free coupon within the comments every few months. www.udemy.com/course/kicad-fem-with-free-software-tools/?couponCode=9C62BBB39D64993A56CD
Can you simulate this after removing the copper pour, using only a ground plane below? It should get rid of the plane reflection?
your modification would then be a microstrip line and has indeed less reflections, so I can confirm this. But be aware that a microstrip has more overall emissions and might cause other problems. via stitching is a good start to contain the fields.
@@panire3 Bogatin showed that ground pour not stitched appropriately increases xtalk between traces. He doesn't talk about radiation a lot since emc is not his focus. So you confirm that CPWG have better Field containment than microstrip?
On the top side (side on which the trace is placed) of a PCB i confirm that CPWG contains the fields better than microstrip in any case that i can possibly think of.
For sideways emissions, use via stitching next to the trace and also along the PCB outline.
BUT: With CPWG i mean one with with via stitches, which I would call "GCPWG" to make sure that stitching vias are used.
A ground pour next to the trace without via stitching (CPWG) could actually be a bad idea, as it increases capacitive coupling between traces which often increases crosstalk. So, I agree with what Mr. Bogatin is saying.
Thanks for great videos! I've been using kicad, FreeCAD and OpenEMS for a long time, but I didn't know that a plugin connecting them existed. Your videos make starting with PCB simulation very easy.
Do you know if there is something similar for thermal simulation? I know that it is possible with OpenFOAM, but I never used this package, and it looks very intimidating.
I think he has some videos on thermal simulation!
Glad it helped! Hope you can use some of the infos for an actual project soon. :)
Regarding thermal simulations, @rick_er2481 is correct, check out the other comments for the thermal stuff. Unfortunately, the thermal videos aren't free, at least for the time being.
@@panire3 wait you have paid content? where? you dont show any links to any other of your work
I dont want to be pushy about the paid content, so i just reply if people ask. With the youtube coupon 9C62BBB39D64993A56CD the course is 13USD: www.udemy.com/course/kicad-fem-with-free-software-tools/?couponCode=9C62BBB39D64993A56CD. If you are on a budget, i share a free link every few months hidden in the comments, so everyone has the opportunity to also go the completely free route. :)
The simulation results are cool, but as such without validation against measured test cupons with same geometry cannot be used to make conclusive claims. This is in fact the key point why commercial simulation toolchains are so expensive - the validation and fitting of the models.
Test case with large floating copper pour around the net and thick substrate dielectric is not representative for most designs in practise - you would either fully remove the pour island, or relatively densely via stitch it to ground.
Generally copper pours on high speed signals routing layers are rarely ever used, the control over routing layer impedance is attained by using thinner dielectric core, single ended signals get wider keepouts to limit coupling. More realistic test scenario for high density PCB layout is stripline design with much thinner dielectric from both sides (in order of 80 to 200 um), for outer layer there won't be any copper pour in surrounding area with few exeptions.
This is an excellent comment and definitely worth reading after watching the video. I completely agree with everything mentioned. Once the channel grows, I’d love to conduct actual reference measurements and compare the results between the commercial and free tools to highlight the strengths and weaknesses of each.
thanks for the video man !
you are doing a good work
Thanks, hope the quality of the videos will be better and better after some more uploads. :)
that's fantastic. Thanks!
Glad you liked it! :)
What js your job in real life? EMC engineer?
hardware design engineer that spent a lot of time in emc chambers.
@@panire3 So cool!
Thanks for the great content...!...I just tried your file exactly as you mentioned, bur for some reason I am not getting the result that you got. Impedance is always above 100 and also getting negative values. Couldn't find what I am doing wrong. Voltage and current values look closer to what you have shown in the video (for the initial part) but the chart has many negative spikes. One thing I have noticed during the process is a warning about unused primitive ( it has mentioned PEC somewhere in the line).
Hi there, I added the executable python script, freecad project file, the macro settings file and also the excel table with the results.
Hope they help you to make it work. Alternatively, you can send me a screenshot of the results or also a screen record of your steps so i can help you troubleshoot
PS: you have to only use the first 1800 values of the table, or in other words only use the values until the end of the trace is reached. The big negative and positive spikes after the 1800th sample are because the signal reaches the end of the trace there. The values after the trace end is reached are not needed anymore for this video example.
you can check out this video regarding TDR method from Eric Bogatin, it will further help you to understand the underlying process used for the simulation.
ua-cam.com/video/yYfkuh4hQ-Y/v-deo.html
Wish this functionality was built-in to KiCAD!
in the kicad forums this is being discussed already for more than 5 years. seems not that easy to implement and/or there are more important things in development right now. so lets keep hoping :-)
Do you have one for S parameter?
Not yet, but it will be ready soon i hope. you will be notified once the video is out if you are subscribed :)
very nice work, thank you
hope it helps for your project/projects. :)
AMAZING!!!
thx for the amazing comment :)