In 2 layer pcb by default 1st layer is power plane 2nd layer is ground plane. What about 4 layer pcb f.cu in1.cu, In2.cu and B.cu which layer Is suitable for power and ground plane?
Fantastic video. Been wondering how to relate frequency simply to rise time. This finally makes some of the rules of thumbs regarding the length of the trace in relation to rise times as well. Love these along with the termination videos, please please please keep them coming.
Hey Phil! I am the avionics lead for the students rocketry team at the University of Washington, and I am self taught in electronics (an aerospace engineering major, not a EE). Your videos have been an invaluable resource in helping me get up to speed on these more advanced electronics concepts and processes, as well as for my members who are often underclassmen who haven’t taken the full EE course load yet. We are currently working through the design and layout for the flight computer, analog input board, and power management system and your videos have been a constant reference in that process. Thank you!
Im pretty sure ive seen all of your videos at this point. They have been an absolute gold mine! Thank you so much for what you do. Any chance we could see a video on high current PCB design? Something like choosing the correct stackup, vias between planes for current handling, and how to calculate the current/temp that each plane could handle?
I think that's a typical 'mistake' of many engineers, just going to the uC config and choosing the fastest option for everything. Not only for the pin speeds but also for communication like I2C, SPI etc. where in 99% of the cases a slower speed will work perfectly without all the added issues that come with higher speed signals. It'd be much wiser to start with the slowest and only increase it when necessary. Also, the spectrum envelopes are very useful for dubugging EMC problems.
@@PhilsLab You have several videos on audio design, but I dont know where to start. I don't really know about designing analog boards circuits and I would love to learn more on the schematic side.
@@PhilsLab thinking in the frequency domain, signal integrity, single point grounding/grounding in general. I design PCBs for my job but it’s mostly digital the most analog intensive thing I do is routing adc singles every now and then but it’s never for critical devices usually for quick test fixtures.
When I was beginning my adventure with electronics, I was under the impression that shorter the rise and fall times, the better. I was proven wrong on many occasions. In particular when I started to work with fast FPGAs. Where even the slightest glitch could cause complete disaster in the design. And sometimes cost me days of troubleshooting. Epecially that there is no way to scope signals inside the FPGA.
Series termination or lowering the driver strength. Whis is better? Which is more effective for overshoot elimitation? And which produces faster edge time?
Depending on how much space you have and how long your traces are, I typically like to add placeholder (0R, or some small resistor) to (most) driver outputs. Sometimes even with lowest drive strength you may still need series resistors (and sometimes a cap afterwards), and on some devices you will not be able to adjust drive strength at all, in which case you may need a series R. Again, for prototypes I like to add them for most driver outputs, test, and then adjust for the production units. Lastly, the cheapest/easiest method - if it is sufficient - is just to reduce the drive strength.
@@PhilsLab Sure, this is clever way - always to add a resistor for prototype. But which way is better? I mean the lower overshoot is a goal. And bigger transition time is a price. So, on which way the transition time increased less?
Waw, very useful! How do changing the location where you probe along the transmission line affect the rise time measured? It should slow down along the transmission line, did you test it?
Thanks! For 'short' transmission lines, such as the ones here, you won't be able to see much difference. But when we'll look at crosstalk in a future video, we'll look at effects in probing positions.
Did you notice that rerducing the drive strength made these 1/8th period artifacts in clock signal? For example at 17:53 Anyone knows what that may be? Is it due to clock frequency division?
@@PhilsLab Yeah, I figured that had to be case because those artifacts stood out in the video. It seems like it's only a couple 100 mVs of crosstalk. Given that it is for an audio application, are you considering going thru another layout revision or is that 100 mVs of crosstalk not something of concern for your audio codec? Also, this real world crosstalk instance might be a good example for a later video covering that subject in detail. 👀
Firstly, it's far less than a 'couple 100mVs'. Secondly, all I2S lines were left at 'very high' drive strength for this video (except for adjusting bit clock). And thirdly, the traces are very short and are spaced out as soon as they exit/enter the pins. I assume it may be something internal to the STM32. And lastly, even this level of crosstalk (without turning down the MCLK drive strength) is typically acceptable on I2S lines (I've seen far worse still working from an SI perspective). But yes, crosstalk is definitely a topic for a future video :)
As always another bummer ! I wanted to know what does strengthening the signal means ? driving with higher current? If so can the same be replicated adding/removing a series resistor ?
Another bummer 😂 Yes, higher drive strength means driving with a higher max. current. E.g. check out a typical STM32 datasheet and look for the OSPEEDRy I/O AC characteristics table. It'll show for what voltages you can get what rise/fall times/frequencies, and from that you can estimate the currents required (from i=C*dV/dt). You can reduce the drive current with a series resistor, yes.
50 Ohms would load the circuit too much. Also, the other hi-Z channel on the scope has 20pF of capacitance, which also would load the circuit too much.
I could be totally wrong, but I'd assume higher edge rates would lead to more power consumption, faster change, more in rush current if there's any input capacitance. I could be totally wrong though, just conjecture
Yes, in general, higher drive strength also means higher power consumptions. The effect is more pronounced the more IO you have and the higher the datarates are.
Thanks for the video! Can you do or link me a Video to impedance? It's still very hard to grasp for me. I don't quite understand why a cable or a trace can have a 50 ohms impedance. What is the 50 ohms about at what frequency? Because if you measure the trace/cable it obviously does not have 50 Ohm (which would be very bad). How to impedance check yourself a trace or cable? Oh and obviously thanks for the video.
Let's start by recommending an video with a great presentation on transmission lines: ua-cam.com/video/yezmCNGTVYU/v-deo.html . To answer your questions the characteristic impedance is frequency independent when using a lossless line. The resistance and conductivity of a cable will introduce a frequency dependent part. A proper cable which is matched at the end will show the 50 ohm at the input. One way to measure this is by measuring the reflected power with an VNA or VSWR meter.
One of my favourite PCB design channels has a video on that: ua-cam.com/video/6_tOOAbuNWg/v-deo.htmlsi=vzn8JKotPaQrGcNJ Also, Robert Feranec with Eric Bogatin have videos discussing this topic. I'll make a video on this in the future as well (but have an old KiCad controlled impedance vid on my channel).
Never clicked this fast on yet another banger video. Thanks for your contribution to the community Phil!
Thank you very much!
In 2 layer pcb by default 1st layer is power plane 2nd layer is ground plane. What about 4 layer pcb f.cu in1.cu, In2.cu and B.cu which layer Is suitable for power and ground plane?
Fantastic video. Been wondering how to relate frequency simply to rise time. This finally makes some of the rules of thumbs regarding the length of the trace in relation to rise times as well. Love these along with the termination videos, please please please keep them coming.
Hey Phil! I am the avionics lead for the students rocketry team at the University of Washington, and I am self taught in electronics (an aerospace engineering major, not a EE). Your videos have been an invaluable resource in helping me get up to speed on these more advanced electronics concepts and processes, as well as for my members who are often underclassmen who haven’t taken the full EE course load yet. We are currently working through the design and layout for the flight computer, analog input board, and power management system and your videos have been a constant reference in that process. Thank you!
Hey, That's awesome! I'm very glad to hear that these videos have been helpful. Hope all goes well with your flight computer design!
I'm amazed how deep your topics go and how accurate your results are! Very useful and inspiring. btw, very nice scope!
Very elegant explanation of the signal integrity concepts. Thanks Phil for this wonderful content.
Thank you very much!
Excellent explanation, now I understand why it is important to keep the drive strength not so high, thank you 😊
Many thanks!
You are Awesome Phil. Thank you so much for keeping my passion alive and educating me in so many area's when I am self taught.
Thank you very much, glad to hear that these videos are helpful! :)
Thanks Phil, really appreciate the time you take to put these videos together. Multiple "light bulb" moments for me in this superb video !
Thanks a lot, I'm glad to hear that!
Sweet video as always - thanks, Phil! I'm jealous of your scope and PCBite setup.
Thanks a lot, Mark - yeah, the scope is pretty awesome!
Thank you so much Phil!
Thanks for watching!
@@PhilsLab Hi Phil can I ask a little question? Would you like to introduce your new Advandec Scope Hardware Course (Maybe with Zynq 7020?)😅😅😅
thank you, very helpful for a project that I'm doing. 👍
Glad to hear that, thanks for watching!
Im pretty sure ive seen all of your videos at this point. They have been an absolute gold mine! Thank you so much for what you do. Any chance we could see a video on high current PCB design? Something like choosing the correct stackup, vias between planes for current handling, and how to calculate the current/temp that each plane could handle?
Awesome information, the timing of this video couldn’t be better! 😉
Glad to hear that, thanks! I haven't forgotten about the design review either, just have a few videos before then!
No worries at all, take your time, Im really loving the content!
I mentioned you in my latest livestream. Love your content!
Thank you very much, Patrick!
Don't tent the ground vias next to your probe points. You can then put the probe ground spring in them.
You're great. Thank you for your content.
Thanks a lot for watching!
Thanks! Great video! This will come in handy the next time I am tempted to sell a kidney for a 2 GHz scope and a 2.5 GHz probe! 😉
Haha yeah, unfortunately they are rather pricey.. but necessary for quite a few parts of my day-to-day work.
Do you think you could do a video about designing a DC motor controller? Your videos have helped me so much!
Glad to hear that, thanks! Yes, I actually have a board made for showing DC motor control in a future video.
I think that's a typical 'mistake' of many engineers, just going to the uC config and choosing the fastest option for everything. Not only for the pin speeds but also for communication like I2C, SPI etc. where in 99% of the cases a slower speed will work perfectly without all the added issues that come with higher speed signals. It'd be much wiser to start with the slowest and only increase it when necessary.
Also, the spectrum envelopes are very useful for dubugging EMC problems.
Grate video. Can also make rise and fall time measurement of RF pulse modulated signal?
Nice gear.
Siglent makes great scopes. Their high voltage and active probes sure are pricey though.
The optional 32ch logic analyzer is a great addition.
Yeah, so far my experience has been pretty good with Siglent. The active probe was the cheapest I could find in this range (even compared to Rigol).
Awesome video, please if you have experience/knowledge do a video on analog PCB design 🙏
Thanks! Any topic in particular?
@@PhilsLab You have several videos on audio design, but I dont know where to start. I don't really know about designing analog boards circuits and I would love to learn more on the schematic side.
@@PhilsLab thinking in the frequency domain, signal integrity, single point grounding/grounding in general. I design PCBs for my job but it’s mostly digital the most analog intensive thing I do is routing adc singles every now and then but it’s never for critical devices usually for quick test fixtures.
When I was beginning my adventure with electronics, I was under the impression that shorter the rise and fall times, the better. I was proven wrong on many occasions. In particular when I started to work with fast FPGAs. Where even the slightest glitch could cause complete disaster in the design. And sometimes cost me days of troubleshooting. Epecially that there is no way to scope signals inside the FPGA.
thanks for that , you are brilliant ;))
Thank you, Harald!
Series termination or lowering the driver strength. Whis is better? Which is more effective for overshoot elimitation? And which produces faster edge time?
Depending on how much space you have and how long your traces are, I typically like to add placeholder (0R, or some small resistor) to (most) driver outputs. Sometimes even with lowest drive strength you may still need series resistors (and sometimes a cap afterwards), and on some devices you will not be able to adjust drive strength at all, in which case you may need a series R. Again, for prototypes I like to add them for most driver outputs, test, and then adjust for the production units. Lastly, the cheapest/easiest method - if it is sufficient - is just to reduce the drive strength.
@@PhilsLab Sure, this is clever way - always to add a resistor for prototype. But which way is better? I mean the lower overshoot is a goal. And bigger transition time is a price. So, on which way the transition time increased less?
Waw, very useful! How do changing the location where you probe along the transmission line affect the rise time measured? It should slow down along the transmission line, did you test it?
Thanks! For 'short' transmission lines, such as the ones here, you won't be able to see much difference. But when we'll look at crosstalk in a future video, we'll look at effects in probing positions.
Did you notice that rerducing the drive strength made these 1/8th period artifacts in clock signal? For example at 17:53
Anyone knows what that may be? Is it due to clock frequency division?
I believe those are crosstalk artefacts from the MCLK edges, which runs at 4x the frequency of the BLCK.
@@PhilsLab Yeah, I figured that had to be case because those artifacts stood out in the video. It seems like it's only a couple 100 mVs of crosstalk. Given that it is for an audio application, are you considering going thru another layout revision or is that 100 mVs of crosstalk not something of concern for your audio codec? Also, this real world crosstalk instance might be a good example for a later video covering that subject in detail. 👀
Firstly, it's far less than a 'couple 100mVs'. Secondly, all I2S lines were left at 'very high' drive strength for this video (except for adjusting bit clock). And thirdly, the traces are very short and are spaced out as soon as they exit/enter the pins. I assume it may be something internal to the STM32. And lastly, even this level of crosstalk (without turning down the MCLK drive strength) is typically acceptable on I2S lines (I've seen far worse still working from an SI perspective). But yes, crosstalk is definitely a topic for a future video :)
As always another bummer ! I wanted to know what does strengthening the signal means ? driving with higher current? If so can the same be replicated adding/removing a series resistor ?
Another bummer 😂 Yes, higher drive strength means driving with a higher max. current. E.g. check out a typical STM32 datasheet and look for the OSPEEDRy I/O AC characteristics table. It'll show for what voltages you can get what rise/fall times/frequencies, and from that you can estimate the currents required (from i=C*dV/dt). You can reduce the drive current with a series resistor, yes.
@@PhilsLab, your video always makes me watch it first whatever I do...that's why said bummer.... LOL
Haha okay, well I'm glad to hear that :D
Why dont you solder on a coax to your PCB back in to 50 ohm on your scope?
50 Ohms would load the circuit too much. Also, the other hi-Z channel on the scope has 20pF of capacitance, which also would load the circuit too much.
Add a 450 or 950 ohm resistor and switch the scope to 50 ohm input, that gives a transmission line probe and will work nicely on a budget
Does the power-consumption of the STM32 also drop with lower edge-rates?
I could be totally wrong, but I'd assume higher edge rates would lead to more power consumption, faster change, more in rush current if there's any input capacitance.
I could be totally wrong though, just conjecture
A faster clock rate definitely increases power consumption, that I'm positive about.
Yes, in general, higher drive strength also means higher power consumptions. The effect is more pronounced the more IO you have and the higher the datarates are.
how to give equvilanent space width(even space) for compoents
why is Teledyne allowing Siglent to cannibalize Lecroy? that active probe; it's the same, only 10x cheaper
Thanks for the video! Can you do or link me a Video to impedance? It's still very hard to grasp for me. I don't quite understand why a cable or a trace can have a 50 ohms impedance. What is the 50 ohms about at what frequency? Because if you measure the trace/cable it obviously does not have 50 Ohm (which would be very bad). How to impedance check yourself a trace or cable?
Oh and obviously thanks for the video.
Let's start by recommending an video with a great presentation on transmission lines: ua-cam.com/video/yezmCNGTVYU/v-deo.html .
To answer your questions the characteristic impedance is frequency independent when using a lossless line. The resistance and conductivity of a cable will introduce a frequency dependent part.
A proper cable which is matched at the end will show the 50 ohm at the input. One way to measure this is by measuring the reflected power with an VNA or VSWR meter.
One of my favourite PCB design channels has a video on that: ua-cam.com/video/6_tOOAbuNWg/v-deo.htmlsi=vzn8JKotPaQrGcNJ
Also, Robert Feranec with Eric Bogatin have videos discussing this topic. I'll make a video on this in the future as well (but have an old KiCad controlled impedance vid on my channel).