Dear Dr.Sadri Thank you for all of the helpful videos I need to save a file from Python on SD card and then transfer these data to DRAM and also BRAM, would you please guide me
Dear Dr.Sadri when you say parallel working AXI DMA in both channels I want to ask one question. I see on documentation that we can define what scheduling method we want to implement to organize data transaction via AXI DMA (in SG mode. for example Round Robin.). But this makes an illusion of parallelism. I want to know about the physical limitation of this. What part or what device is making it impossible to have true parallel running channels in AXI DMA. I really see that on my device there is certain some priorities defined when running even in Direct Register mode. Thanks in advance.
Thanks for the video. I checked the axidma with ethernet example (xilinx) with scatter gather mode and found that they use only one rxbd for receiving a packet, hence, if I say want to receive 10 packets continuously then in that case should the 10th BD point to the 1st BD. As only single BD is used for a packet, how will the concept of tail and head pointer be valid? thank you.
ok i have not seen their design but one bd can point to itself and dma can be always busy processing this one single bd. thats once a transfer task is done it starts again. now this can be beneficial in a design where you want to do a completely unique transfer with fixed address and size values over and over...
Mohammadsadegh Sadri I am trying to create a design for my Image Processing research on Virtex-7 board, and have no clue how to write a software program for Microblaze. Can you please redirect me to something that can be of help to me.
+Mohammadsadegh Sadri I am using it to program the AXI DMA, which stores the AXI Stream output of my pipeline into the DDR memory. I plan to use the AXi DMA in a Scatter Gather mode.
+Nitin Chugh axi vdma you mean or you plan to use the axi dma directly? in any case there is obviously the microblaze processor reference guide from xilinx that you should have a look at and then another nice document Xilinx os and libraries document collection i beleieve with these two and available examples you should be able to do the task
many thank for the wonderful video. i succeed to do example design in this video by using xmd. but when i created application to the test_1, and after that i read the address it's doesn't work the content in address didn't overwrite by the counter, however it's stay 0xBBB what is the different between xmd and application with template Hello World thanks
Hi@@MohammadSSadri, Thanks for your gread Videos and effort. I'm living same problem with @pini malul. I think clock is not running. I did everything what you say in your video. ILA prob also gets nothing. I could not understand, what you mean with "cpu cache". I followed this steps: connect arm hw fpga -f project1.bit ps7_init ps7_post_config In a thread they have already talked about same problem and ps7_post_config was solved problem, but my problem continue. Regards, Saban
Hi Mohammed, I solved my clock problem. I do not know what is the exact reason, but I have already installed Vivado 2016.2 and you used 2015.1 in your video. I installed your and I create design by using your create script again and it solved the problem.
Hello, Do you have the part III of lesson 10? the software part for the data transfer? I have already made the donation but in the dropbox folder I cant find the part III. Would you please help me on this regard , how can I find the source codes for part III?
hi, just convert the tcl script that you have through your account into c code, it is direct and easy, mwr turns into xil_out and mrd into xil_in let me know if you need further help. i have design examples for AXI DMA Scatter Gather mode when running Linux on the arm host and using a custom kernel level driver, those however are available at a fair cost.
Dear Dr. Sadri, Thanks for the video. I would like to buy the third video in case that there are description for the C code as well (for the software). However, I am not sure how to reach out to you for this matter.@@MohammadSSadri
Dear Dr.Sadri
Thank you for all of the helpful videos
I need to save a file from Python on SD card and then transfer these data to DRAM and also BRAM, would you please guide me
Dear Dr.Sadri when you say parallel working AXI DMA in both channels I want to ask one question.
I see on documentation that we can define what scheduling method we want to implement to organize data transaction via AXI DMA (in SG mode. for example Round Robin.). But this makes an illusion of parallelism. I want to know about the physical limitation of this. What part or what device is making it impossible to have true parallel running channels in AXI DMA.
I really see that on my device there is certain some priorities defined when running even in Direct Register mode.
Thanks in advance.
Thanks for the video. I checked the axidma with ethernet example (xilinx) with scatter gather mode and found that they use only one rxbd for receiving a packet, hence, if I say want to receive 10 packets continuously then in that case should the 10th BD point to the 1st BD. As only single BD is used for a packet, how will the concept of tail and head pointer be valid? thank you.
ok i have not seen their design but one bd can point to itself and dma can be always busy processing this one single bd. thats once a transfer task is done it starts again. now this can be beneficial in a design where you want to do a completely unique transfer with fixed address and size values over and over...
can you please refer me to part III. Cannot find it anywhere
that is to be created...
Mohammadsadegh Sadri I am trying to create a design for my Image Processing research on Virtex-7 board, and have no clue how to write a software program for Microblaze. Can you please redirect me to something that can be of help to me.
+Nitin Chugh what is the microblaze supposed to do in your inage processing pipeline?
+Mohammadsadegh Sadri
I am using it to program the AXI DMA, which stores the AXI Stream output of my pipeline into the DDR memory.
I plan to use the AXi DMA in a Scatter Gather mode.
+Nitin Chugh axi vdma you mean or you plan to use the axi dma directly?
in any case there is obviously the microblaze processor reference guide from xilinx that you should have a look at
and then another nice document Xilinx os and libraries document collection
i beleieve with these two and available examples you should be able to do the task
Really cool, I'm starting as well a Vivado HLS training this week
great job
Thank you for the video.
Is there an advantage to having the BDs stored in BRAM vs. the DDR3?
Is it faster in BRAM?
Hi Kalhana, access to bram has lower and fixed latency.
many thank for the wonderful video.
i succeed to do example design in this video by using xmd.
but when i created application to the test_1, and after that i read the address it's doesn't work
the content in address didn't overwrite by the counter, however it's stay 0xBBB
what is the different between xmd and application with template Hello World
thanks
mind the cpu cache!
Hi@@MohammadSSadri,
Thanks for your gread Videos and effort.
I'm living same problem with
@pini malul.
I think clock is not running.
I did everything what you say in your video.
ILA prob also gets nothing.
I could not understand, what you mean with "cpu cache".
I followed this steps:
connect arm hw
fpga -f project1.bit
ps7_init
ps7_post_config
In a thread they have already talked about same problem and ps7_post_config was solved problem, but my problem continue.
Regards,
Saban
Hi Mohammed,
I solved my clock problem. I do not know what is the exact reason, but I have already installed Vivado 2016.2 and you used 2015.1 in your video.
I installed your and I create design by using your create script again and it solved the problem.
how to download the designed wrapper ??
designed wrapper? if you mean access to source code of videos, they are available upon a donation.
Hello, Do you have the part III of lesson 10? the software part for the data transfer? I have already made the donation but in the dropbox folder I cant find the part III. Would you please help me on this regard , how can I find the source codes for part III?
hi, just convert the tcl script that you have through your account into c code, it is direct and easy, mwr turns into xil_out and mrd into xil_in
let me know if you need further help.
i have design examples for AXI DMA Scatter Gather mode when running Linux on the arm host and using a custom kernel level driver, those however are available at a fair cost.
Dear Dr. Sadri,
Thanks for the video. I would like to buy the third video in case that there are description for the C code as well (for the software). However, I am not sure how to reach out to you for this matter.@@MohammadSSadri
Awesome lection, God bless you !!!
Good explanation