Lets Learn Verilog with real-time Practice with Me | Introduction to Vectors | DAY 4

[@middegovarshikayadav6469]

*Net doesn't store any value where as Reg can store
*Net is nonsynthesisable
Reg is synthasisable
*Net is conteneous assignment
Reg is procedural assignment

[@NostalgiaT]

what does nonsynthesisable or syntehtsizeable mean>

[@intelligence6743]

vector 0 quesstion answer is not showing right in mine pc i am doing same on the same site and same coding but the answer is not success

[@renukak9138]

net will notstore, it is just change its state when we give an input,
reg will store or hold the value untill we give next

[@chanaganinarender1003]

What are the opportunity for the ECE students in the month of September. Could any one say or provide the link to me

[@rohanam4959]

[at time 20:06] why do you declare vectors in the right side i.e in[15:8] ,,,,,,, why not [15:8]in? in assign statement

[@ranjanyadav9011]

that's how you are supposed to access the bits of the vector created in verilog

[@soukaryabiswas7852]

[At time 6:36] Can you please explain why the timing diagram of the input signal(vec) is represented in that way?
I see that it's a combination of three(independent) input signals but why are there only 2 lines in the diagram?

[@whyRD]

Oky sure will explain in day 6 or 7

[@soukaryabiswas7852]

@@whyRD Thanks a lot Dada🙏

[@ASPIRANT-hw1qe]

okay iam here again for day 4

[@whyRD]

Need you here everyday 😃

[@DevendraSingh-dt6zl]

NETs is not hold data and its default value Z
Registers is hold data and its default value X

[@hardiksarraf1221]

Thank you bhaiya ✨✨

[@nissanbiswas8432]

very very helpful Thank you 👍

[@chanaganinarender1003]

Could any one post the code for vector 1

[@sreelakshmip736]

Thank you sir☺

[@dhanalakshmi5930]

Thank you soooooo much sir

[@RualsbVdbam]

❤

[@uddhavaher4463]

Thank you so much @whyRD