@Asianometry your labeling of NMOS and PMOS at 5:55 is backwards. The labeling of MOSFET types is done by the doping type of the source and drain, not the body. So an NMOS sits in a PWELL and has n-type doped source and drain, while a PMOS sits in an NWELL with p-type doped source and drain. (Though you are correct in stating that the formal definition of MOSFET type is based on the carrier type when the inversion channel is formed. But its much easier to tell for MOSFETs by looking at the doping in the source and drain. The issue would be compounded if we were looking at enhancement mode vs depletion mode, or the other exotic MOSFET types, but most of the time when people say MOSFETs, they're referring to enhancement mode.)
I mention this in most of his semicon videos, but I also think it would behoove him very much to update the color scheme on his standard CMOS cartoon to make the Source and Drain the same color for each transistor. It is confusing at best, and misleading at worst, to make the Source of NMOS and PMOS the same color, and Drain of N and P the same color. The source and drain of each transistor, or in reality the “active areas” of each transistor are, effectively, equivalent - built of the same materials and doping and process steps. The only thing that makes one a Source and one a Drain is how they are hooked up to the interconnects and power signals based on logic design. So, I think it would be much better to, for example, set both of the N+ doped Source and Drain of the NMOS to yellow, then both of the P+ doped Source and Drain of the PMOS to magenta. Or, taking it one more step, make all of the P-type silicon (including the P type substrate, P wells, and P+ doped active areas) different shades of, for example, red or purple. Then all of the N type silicon (including N wells and N+ doped areas) different shades of yellow or orange or something. Then use other colors like greens, blues, grays, etc for metals and oxides
@@BillAnt It's certainly possible NVidia could end the same way, but at present the big difference between the two is Intel is building fabs and Nvidia is fab-less. Not the greatest of comparisons. Also Jensen Huang's strategy is to build out an AI ecosystem and be the biggest player in that market. For example, they've developed CUDA software to run on their hardware, ensuring future recurring revenue. We'll see how successful they are but I expect them to be dominant for at least a couple of years. For the size of the orders it's going to take time for all these investments to actually get built out and longer still to see if it's profitable. My time horizon for them is 3-5 years to show they aren't a flash-in-the pan CAPEX spend from the rest of the tech sector. We'll see.
Bob Swan insisted that 10nm should both be an aggressive shrink of 2.3x instead of the usual cadence of 1.7x AND it should be cheaper to produce (by omitting EUV) than 14nm. By the time 10nm actually started ramping TSMC was well ahead on their N5 node that was denser and cheaper using EUV. They did better in two steps than Intel did in one, and they did it faster. Intel's next generation Arrow Lake will "initially" be made on TSMC N3 "until Intel can ramp production" of their own version. This is what happens when you sent a bean counter to do an engineers job.....
@@phuang3 It could be done. That is precisely how their 10nm works. But it's a more expensive node today than TSMC N3 is. Intel 10nm uses SO many double and quadruple patterning steps that any gain in not shelling out for EUV machines gets lost many times over in wash and etch steps.
@@andersjjensen I was wrong. Intel aimed for 2.7x shrink from their 14nm node. I doubt they did it. There is rumour that Intel changed their goal secretly.
@@phuang3 They aimed for 2.7x but reached 2.3x. Since Intel does foundry service now so the density of their 10nm is publicly known. They have an ungodly amount of capacity for it, that they're moving off themselves now, and still no customers because it is so expensive. It was a recurring topic at yesterdays investor call......
@@TheOneAndOnlySatan - Down 55% year to date... pretty sad for a one time high flying leader. Remember when "Intel Inside" was considered the best? ;)
Fascinating, interesting,...but i gotta admit most of the time i'm watching these 'nanometer-docs' with raised eyebrows going '' holy f**ing sh*t '' in amazement while understanding 10% of it. Thanks a lot! Keep 'em coming
Every middle-class American must encounter this debilitating dilemma anytime they trek past their white-picket fence gate, thinking "dammit, it did it again."
The detailed exploration of transistor scaling challenges is impressive. It's clear you've put a lot of effort into making these concepts understandable.
How about a new video, about TSMC newer 7nm and possibly 4nm technologies. How do they get the gate insulators down to half-nanometer without defects. Also Source and Drain patches have to be so thin, that the resistance paths have to be huge. That has to hurt the Speed available. We should be getting into R-L-C speed limits, unless they put in transmission line artifacts. The throughput has to be horrible.
Error correction due to quantum effects and defects, along with thermal problems related to feature density have been limiting speed for more than a decade. This is part of why the 28nm node remains so sucessful and is still used for most commodity class chips. It was the smallest node that wasn't strongly effected by these problems. This is also why 32nm AMD chips (FX-83xx) continue to hold the world records for overclocking more than a decade after release. (Measured in frequency, not task speed.)
@@mytech6779 Also seeing similar problems for "radiation resistance" in these chips. Especially for home-brew mini & microsats in orbit. Also in high-altitude balloon projects.
A wonderful explanation of some of the most complex technological inventions. I wonder though, how large the audience might be, that actually understands everything you tell them. But that's no critique. Please continue amazing us with your fine videos! 👌👍 P.S. as a retired semiconductor circuit designer, I had personal experience with many twists and turns of this breathtaking story.
No, Cheng is correct. In order to turn on a PMOS, you have to invert a moderately doped n type bulk to become p and thus create a conductive p type channel. The picture would be correct if the PMOS and Nmos labels are swapped or if the substrate is n doped
A remarkably diverse industry, Silicon Valley. We have these scientists and engineers, working at an atomic level to change the behaviour of elements, geniuses pushing physics to the limits, then we have the Tech Bro chuds who want to become billionaires with another delivery app.
Thanks, Jon. That conclusion is particularly hard to hear today, 01 Aug 24, after Intel's quarterly earnings debacle, massive layoff, and dividend cancellation. 💸 😮💨✌️
Worth noting 40nm was TSMC's first implementation of stain, and 28nm is second generation strain. Also intel 45nm used tungsten for the gate metal not Aluminum.
I believe this may be my favorite channel now. Who the heck else would ever bother to explain any of this stuff to us regular folks unless we were paying to earn a degree?
I'll be picking up a bunch of Intel stock soon. They are behind but never out of the fight. They suspended their dividend so they can focus on innovation. Enough pandering to shareholders! That's why AMD was able to jump ahead, less pandering and more innovating. Great video by the way!
One of the reasons the AMD HD 5000 series was so good compared to the GTX 480 was because AMD used the Radeon HD 4770 as a test bed for TSMC's 40nm process first, and discovered that it had yield issues due to weak vias. This wasn't much of a problem for the 4770 itself, because of its small die size, but could have been a problem for the 5870. So, AMD worked around that by doubling up on the vias, at a small cost of die area, but this gave them redundancy, and prevented yield issues. Whereas for Nvidia, the GTX 480 was the first time they used TSMC's 40nm process, and since they were making the die size so much larger, they had significant yield issues, and is probably why they only used 480 of the 512 shaders.
fermi was a terribly power hungry architecture, that's what really hurt nvidia, still as it usually happens nvidia still out sold amd by a good margin.
Your videos are excellent and remind me how little I actually learned in college in the early 80s. With one or two exceptions my professors epitomized the phrase, "Those that can't, teach." Every potential electrical engineering student would do well to watch all of your videos.
Worth remembering that the Intel 10nm debacle after that, started because they were (over)confident they could merge 3 gens of innovations into the same node. They basically wanted to do the equivalent of a 7nm EUV made node but without EUV... needless to say, turns out it was a bridge too far. Since it never yielded properly (to this day, 10nm Intel wafers are rumored to still be outrageously expensive and Intel making basically 0$ on any CPU they sell made on them) it got them stuck on the famous 14nm+++++ era which they still struggle to get out of. Every new design they talk about either get cancelled altogether, or is made at TSMC instead.
20:50 > 28nm > A pinnacle of planar transistor technology If only you knew how awful it is for analog, much more so than even FinFET in my opinion. Body effect and DIBL are horrible in this one.
Man your vids are always a good shit's length. I dunno anything about this stuff but that's why it's so engrossing to learn about while dropping logs. You the best
wrong substrate in @6:03 NMOS is npn PMOS is pnp, suibstrate should be n-type sillicon. you are drawing nmos constructed in a "n-well" which is not correct
I love when video-games (modded usually) is actually teaching me real science before I figure out that it's actually real. Insane. I made circuits in Pyanodon (in Factorio) and I accidentally already knew a lot of the vocabulary here, surprisingly. 😂 "Oooh it's not a game thing???"
The GF100 chip name stands for Geforce Fermi 100 iirc. The second letter at that time being the architechture signififier. Similarlt there was rhe GM100 for maxwell and so on.
Very cool, i had no idea about the egineering challengins in CPU design, the tech media only foucues on the competion, but the real competiton is nature and its challenges, no engineer is thinking about "crushing" any kind of competition they'r trying to solve real problems.
Nobody knows anything for certain about it. There is good indication that the oxidation contamination at the Arizona fab only affected Sapphire Rapids server CPUs, and that the Raptor Lake and Raptor Lake Refresh failure are solely due to the ringbus getting cooked. But it is just that: good indication. Not outright proof.
In 40 years there will probably be a 2 hour retrospective made by a youtuber how this "crisis" contributed to the inevitable spiraling downfall of Intel
Started watching. Hoping it goes into real world examples like "if you have to close 3 physical gates with people trying to rush into a castle, how does the order you shut them change the outcome". And if its that... the bottom half of your human donut hole has multiple sphincters. And I hope, whatever choice we picked as a society for transistors, happens to align with the order our body chooses to open or close those sphincters. Bc shtposting is life. And so is the internet. And I want to have another way to connect them in my weird ADHD brain.
Why not Gate central ie drain at the top, source at the bottom, pillar GAAFET. Especially with 13.5nm, lets say the pillar is 28nm radius, 9F2 for 1 transistor (giving room for vias), you essentially get 2BILLION T/mm2 (ie 3nm x10) Im genuinely curious why it isnt a thing, at the very least for SRAM
idk if it's relevant to the channel, but could you make a video providing insight on the recent mass layoffs in Intel? The reasons behind it n stuff, beceause it seems absurd considering that the government is investing a lot into their fabs
lets see: they design many more dies than the competition, and intel's dies are massive in comparison making their products much more expensive both to produce as well as to design. their reliability record is now on public trial due to pushing their chips too hard. their internal foundry has been loosing ground to TSMC, their joining of the gpu market has mostly failed, they still have 100k workers vs AMDs ~25k. yes they might be getting some grants but gov money isn't something to trust and at the Rate these kinds of companies burn R&D funds it wont last long. they need severe cost cutting measures yesterday and they dont seem to be doing them.
Intel squandered their lead indeed. 14nm++++++++ is ridiculous. But then again, they made a huge amount of money until recently so investing $400+M in the EUV machine + tooling is not that big of a deal and a chance to leapfrog TSMC into 1.8nm.
Yes, the technological downfall of Intel is the greatest industry miracle. The did 45nm with hybrid gate last (highk was gate 1st like) and double pattering as iARF was not ready before the other came with a still polySiON node. TSMC followed in 32/28 but Intel had full gate last already at 32. Everyone tried to copy Intel on 22, but boom Intel presented FinFET. They were always ahead. Every 2-3 years a new full node. And then 6-7 years not solving the issues in 10nm!
Theses things seem to be too complicated too exist so I don’t think it’s possible… I am just curious about how I am supposed to believe that given that I am watching this on my iPhone 😅😅😅😅
28nm is the oldest node still viable for modern gaming and general consumer use. Where it fails in consumer CPUs is in things like modern video encoding, everything else, still can do, and probably could still be made to do. And it's been what, 13 years?
It would have been hilarious if you had said "by the Asianometry patreon, early access members get to see videos first...or last." Sorry, sorry, I'll see myself out.
No it is Metal-Oxide-Semiconductor. It's suppose to refer to the material stackup when taking a cross section of the transistor at the midline, which is right through the gate, oxide, and body of the transistor where the channel forms during inversion.
I struggle with this every morning - too often I'm trapped in the garden, unable to travel to work.
same bro, even imagining how the atoms are dancing around 😂
I think the joke was that they struggle opening their gate.@@fruchtsafarigonzo364
🤣 real
I was with everything he said until 10 seconds in.
This used to happen to me, till I discovered the Roman empire.
"Such an amazing lead, so quickly squandered."
Intel Now = AMD in 2002
@Asianometry your labeling of NMOS and PMOS at 5:55 is backwards. The labeling of MOSFET types is done by the doping type of the source and drain, not the body. So an NMOS sits in a PWELL and has n-type doped source and drain, while a PMOS sits in an NWELL with p-type doped source and drain. (Though you are correct in stating that the formal definition of MOSFET type is based on the carrier type when the inversion channel is formed. But its much easier to tell for MOSFETs by looking at the doping in the source and drain. The issue would be compounded if we were looking at enhancement mode vs depletion mode, or the other exotic MOSFET types, but most of the time when people say MOSFETs, they're referring to enhancement mode.)
I mention this in most of his semicon videos, but I also think it would behoove him very much to update the color scheme on his standard CMOS cartoon to make the Source and Drain the same color for each transistor. It is confusing at best, and misleading at worst, to make the Source of NMOS and PMOS the same color, and Drain of N and P the same color. The source and drain of each transistor, or in reality the “active areas” of each transistor are, effectively, equivalent - built of the same materials and doping and process steps. The only thing that makes one a Source and one a Drain is how they are hooked up to the interconnects and power signals based on logic design.
So, I think it would be much better to, for example, set both of the N+ doped Source and Drain of the NMOS to yellow, then both of the P+ doped Source and Drain of the PMOS to magenta. Or, taking it one more step, make all of the P-type silicon (including the P type substrate, P wells, and P+ doped active areas) different shades of, for example, red or purple. Then all of the N type silicon (including N wells and N+ doped areas) different shades of yellow or orange or something. Then use other colors like greens, blues, grays, etc for metals and oxides
@@JoeLion55 Very good points and I agree.
Man, that ending had the same vibe that documentaries about GM's downfall in the Malaise era have.
An coincidentally Intel's stock has fallen 55% year to date.... sad. Wonder if NVida will end the same some time in the future. heh
@@BillAnt It's certainly possible NVidia could end the same way, but at present the big difference between the two is Intel is building fabs and Nvidia is fab-less. Not the greatest of comparisons. Also Jensen Huang's strategy is to build out an AI ecosystem and be the biggest player in that market. For example, they've developed CUDA software to run on their hardware, ensuring future recurring revenue. We'll see how successful they are but I expect them to be dominant for at least a couple of years. For the size of the orders it's going to take time for all these investments to actually get built out and longer still to see if it's profitable. My time horizon for them is 3-5 years to show they aren't a flash-in-the pan CAPEX spend from the rest of the tech sector. We'll see.
@@methos-ey9nf - Who knows, once this AI hype blows over, maybe some entirely different tech will come out.
"Patrion, first access, blah blah, you know the pitch"
Glad to see the creators are getting tired of the same line every time also 🤣🤣🤣
At least it's short and sweet, unlike those channels that drag out their sponsorships for 3 minutes.
Bob Swan insisted that 10nm should both be an aggressive shrink of 2.3x instead of the usual cadence of 1.7x AND it should be cheaper to produce (by omitting EUV) than 14nm. By the time 10nm actually started ramping TSMC was well ahead on their N5 node that was denser and cheaper using EUV. They did better in two steps than Intel did in one, and they did it faster. Intel's next generation Arrow Lake will "initially" be made on TSMC N3 "until Intel can ramp production" of their own version. This is what happens when you sent a bean counter to do an engineers job.....
10nm with 2.3x shrink and DUV are of course better financially, but it can't be done. This decision almost killed Intel.
@@phuang3 It could be done. That is precisely how their 10nm works. But it's a more expensive node today than TSMC N3 is. Intel 10nm uses SO many double and quadruple patterning steps that any gain in not shelling out for EUV machines gets lost many times over in wash and etch steps.
It was Brian K. not bob??
@@andersjjensen I was wrong. Intel aimed for 2.7x shrink from their 14nm node. I doubt they did it. There is rumour that Intel changed their goal secretly.
@@phuang3 They aimed for 2.7x but reached 2.3x. Since Intel does foundry service now so the density of their 10nm is publicly known. They have an ungodly amount of capacity for it, that they're moving off themselves now, and still no customers because it is so expensive. It was a recurring topic at yesterdays investor call......
From Swiss watches to atomic layer IC processes... never boring here.
Swiss watches... zzzzzz
Atomic layering... woohoo
Coming off of Intel's Q2 results, this hits hard
It really does
@@TheOneAndOnlySatan - Down 55% year to date... pretty sad for a one time high flying leader. Remember when "Intel Inside" was considered the best? ;)
@@BillAnt thanks for the intel gigglr
Fascinating, interesting,...but i gotta admit most of the time i'm watching these 'nanometer-docs' with raised eyebrows going '' holy f**ing sh*t '' in amazement while understanding 10% of it. Thanks a lot! Keep 'em coming
I think chip production is about as close as you can get to wizardry on a mass production scale
Every middle-class American must encounter this debilitating dilemma anytime they trek past their white-picket fence gate, thinking "dammit, it did it again."
The detailed exploration of transistor scaling challenges is impressive. It's clear you've put a lot of effort into making these concepts understandable.
The Chinese word at about 14:30 means 'complicated' or perhaps 'trouble' depending on context.
Indeed, in this context it'll probably be "bother" or "bothersome" - 麻煩 Máfan
it's more like "annoying for its complexity", i.e. complicated with a stressed implication that one is unwilling to deal with it.
I though the said no fun lol, didn't realize he was chinese
How about a new video, about TSMC newer 7nm and possibly 4nm technologies. How do they get the gate insulators down to half-nanometer without defects. Also Source and Drain patches have to be so thin, that the resistance paths have to be huge. That has to hurt the Speed available. We should be getting into R-L-C speed limits, unless they put in transmission line artifacts. The throughput has to be horrible.
Spy detected
Error correction due to quantum effects and defects, along with thermal problems related to feature density have been limiting speed for more than a decade. This is part of why the 28nm node remains so sucessful and is still used for most commodity class chips. It was the smallest node that wasn't strongly effected by these problems. This is also why 32nm AMD chips (FX-83xx) continue to hold the world records for overclocking more than a decade after release. (Measured in frequency, not task speed.)
@@mytech6779 Also seeing similar problems for "radiation resistance" in these chips. Especially for home-brew mini & microsats in orbit. Also in high-altitude balloon projects.
Now Intel is laying off 10k workers and have a untold number of failing cpus 😔☠️
I know it's sad, especially for kids who grew up using and knowing only Intel chips. 😔
We were working on Si-Ge at MIT in the early 1980’s.
A wonderful explanation of some of the most complex technological inventions. I wonder though, how large the audience might be, that actually understands everything you tell them. But that's no critique. Please continue amazing us with your fine videos! 👌👍 P.S. as a retired semiconductor circuit designer, I had personal experience with many twists and turns of this breathtaking story.
(note to self)
2:44 -> reason why we use polysilicon instead of aluminium as a gate. and why poly gates make the process self aligning.
6:03 NMOS means inversion electron channel and it is on p-type silicon, PMOS is on N-type silicon. so it should be opposite in that page.
*EDIT* I was mistakes and you are correct.
No, Cheng is correct. In order to turn on a PMOS, you have to invert a moderately doped n type bulk to become p and thus create a conductive p type channel. The picture would be correct if the PMOS and Nmos labels are swapped or if the substrate is n doped
@@Saypayaa Thank you for the correction, I didn't even notice the label at the bottom!
A remarkably diverse industry, Silicon Valley. We have these scientists and engineers, working at an atomic level to change the behaviour of elements, geniuses pushing physics to the limits, then we have the Tech Bro chuds who want to become billionaires with another delivery app.
Small mistake at 3:54, in the 130nm node the GOX was 2.5nm not 25nm thick.
Reference the Wilmington News Journal. Bad ass.
Thanks, Jon. That conclusion is particularly hard to hear today, 01 Aug 24, after Intel's quarterly earnings debacle, massive layoff, and dividend cancellation. 💸 😮💨✌️
Worth noting 40nm was TSMC's first implementation of stain, and 28nm is second generation strain. Also intel 45nm used tungsten for the gate metal not Aluminum.
Loved "Bla bla bla You know the pitch"😂
Self knowledge! 😅✌️😎
I thought it was very mildly in poor taste.
I believe this may be my favorite channel now. Who the heck else would ever bother to explain any of this stuff to us regular folks unless we were paying to earn a degree?
Yes! aluminium pronounced right!
What's that? Is it similar to aluminum?
that Nehalem (ne-Hay-lum) was brutal
fabulous work! Will save it for an energetic morning to learn!
I'll be picking up a bunch of Intel stock soon. They are behind but never out of the fight. They suspended their dividend so they can focus on innovation. Enough pandering to shareholders! That's why AMD was able to jump ahead, less pandering and more innovating. Great video by the way!
gonna shit my pants while watching this
So gate first?
Shy guy drank too much paint through a straw you get what you get 💀
yeah hes shitmaxxing, brownpilled as hell
One of the reasons the AMD HD 5000 series was so good compared to the GTX 480 was because AMD used the Radeon HD 4770 as a test bed for TSMC's 40nm process first, and discovered that it had yield issues due to weak vias. This wasn't much of a problem for the 4770 itself, because of its small die size, but could have been a problem for the 5870.
So, AMD worked around that by doubling up on the vias, at a small cost of die area, but this gave them redundancy, and prevented yield issues.
Whereas for Nvidia, the GTX 480 was the first time they used TSMC's 40nm process, and since they were making the die size so much larger, they had significant yield issues, and is probably why they only used 480 of the 512 shaders.
fermi was a terribly power hungry architecture, that's what really hurt nvidia, still as it usually happens nvidia still out sold amd by a good margin.
Your videos are excellent and remind me how little I actually learned in college in the early 80s. With one or two exceptions my professors epitomized the phrase, "Those that can't, teach." Every potential electrical engineering student would do well to watch all of your videos.
To this day it’s still amazing that things so small can be reliable
4:49 Love how you had to specify "...then unquestionably...", given their current problems.
Worth remembering that the Intel 10nm debacle after that, started because they were (over)confident they could merge 3 gens of innovations into the same node.
They basically wanted to do the equivalent of a 7nm EUV made node but without EUV... needless to say, turns out it was a bridge too far.
Since it never yielded properly (to this day, 10nm Intel wafers are rumored to still be outrageously expensive and Intel making basically 0$ on any CPU they sell made on them) it got them stuck on the famous 14nm+++++ era which they still struggle to get out of. Every new design they talk about either get cancelled altogether, or is made at TSMC instead.
That’s a gate question.
Almost thought this was a Protoss build order
but its never gate first, you need that pylon
Zerg rules.
@@ZapOKill nexus first my dude
Why are we even discussing this? I thought 512kb was all we'd ever need
20:50
> 28nm
> A pinnacle of planar transistor technology
If only you knew how awful it is for analog, much more so than even FinFET in my opinion. Body effect and DIBL are horrible in this one.
Love the content. You should put the PC in another room while you record.
Man your vids are always a good shit's length. I dunno anything about this stuff but that's why it's so engrossing to learn about while dropping logs. You the best
Please eat some more fiber and drink more water
wrong substrate in @6:03 NMOS is npn PMOS is pnp, suibstrate should be n-type sillicon. you are drawing nmos constructed in a "n-well" which is not correct
I love when video-games (modded usually) is actually teaching me real science before I figure out that it's actually real. Insane. I made circuits in Pyanodon (in Factorio) and I accidentally already knew a lot of the vocabulary here, surprisingly. 😂 "Oooh it's not a game thing???"
8:42 FULLMLETAL ALCHEMIST MENTIONED!!!!
hooly didn't know that this was posted like half and hour ago
very indepth and interesting look at transistor design, thanks!
I greatly the full metal alchemist reference. Major kudos!
The GF100 chip name stands for Geforce Fermi 100 iirc. The second letter at that time being the architechture signififier. Similarlt there was rhe GM100 for maxwell and so on.
Very cool, i had no idea about the egineering challengins in CPU design, the tech media only foucues on the competion, but the real competiton is nature and its challenges, no engineer is thinking about "crushing" any kind of competition they'r trying to solve real problems.
Can you make a video on the Raptorlake failures?
Nobody knows anything for certain about it. There is good indication that the oxidation contamination at the Arizona fab only affected Sapphire Rapids server CPUs, and that the Raptor Lake and Raptor Lake Refresh failure are solely due to the ringbus getting cooked. But it is just that: good indication. Not outright proof.
In 40 years there will probably be a 2 hour retrospective made by a youtuber how this "crisis" contributed to the inevitable spiraling downfall of Intel
@@FLAXMSassuming youtube is still a thing in 40 years is bold 😀
In the UK, Prescott was a fat minister of parliament famous for punching members of the electorate.
That's pretty badass. Seems like y'all might need another man like him.
Never heard of this
We must get the EOT that Grammy!
Started watching. Hoping it goes into real world examples like "if you have to close 3 physical gates with people trying to rush into a castle, how does the order you shut them change the outcome".
And if its that... the bottom half of your human donut hole has multiple sphincters. And I hope, whatever choice we picked as a society for transistors, happens to align with the order our body chooses to open or close those sphincters.
Bc shtposting is life. And so is the internet. And I want to have another way to connect them in my weird ADHD brain.
when the engineering and science is so deep it can be passed off as lore
Glitch ?
"Finding an Alternative" shows up twice @10:28 & @10:30
I love the random 麻烦
Why not Gate central ie drain at the top, source at the bottom, pillar GAAFET.
Especially with 13.5nm, lets say the pillar is 28nm radius, 9F2 for 1 transistor (giving room for vias), you essentially get 2BILLION T/mm2 (ie 3nm x10)
Im genuinely curious why it isnt a thing, at the very least for SRAM
Thanks as always from Canberra AU.
idk if it's relevant to the channel, but could you make a video providing insight on the recent mass layoffs in Intel? The reasons behind it n stuff, beceause it seems absurd considering that the government is investing a lot into their fabs
lets see:
they design many more dies than the competition, and intel's dies are massive in comparison making their products much more expensive both to produce as well as to design.
their reliability record is now on public trial due to pushing their chips too hard.
their internal foundry has been loosing ground to TSMC,
their joining of the gpu market has mostly failed,
they still have 100k workers vs AMDs ~25k.
yes they might be getting some grants but gov money isn't something to trust and at the Rate these kinds of companies burn R&D funds it wont last long.
they need severe cost cutting measures yesterday and they dont seem to be doing them.
2024 here. Whatever we got righ now works great. If you need more, just use 2 of them.
to gate first, or to gate last, that is the question
Intel squandered their lead indeed. 14nm++++++++ is ridiculous. But then again, they made a huge amount of money until recently so investing $400+M in the EUV machine + tooling is not that big of a deal and a chance to leapfrog TSMC into 1.8nm.
Wow. Just wow.
I dig the semiconductor vids
This topic 7K views in 4 hours on UA-cam?!
Amazing ! I thought 1% of that would be reasonable in this time frame.
Onya, Jon.
You tell a great story of computer technology and development.
And I'm but one of your avid audience.
Playing all the hits on this channel! lol
Gate often
Intel got their tech from a recovered alien spacecraft.
And the price of Intel dropped by 30% on the same as this video comes out. Sad...
Yes, the technological downfall of Intel is the greatest industry miracle.
The did 45nm with hybrid gate last (highk was gate 1st like) and double pattering as iARF was not ready before the other came with a still polySiON node. TSMC followed in 32/28 but Intel had full gate last already at 32. Everyone tried to copy Intel on 22, but boom Intel presented FinFET. They were always ahead. Every 2-3 years a new full node. And then 6-7 years not solving the issues in 10nm!
Theses things seem to be too complicated too exist so I don’t think it’s possible… I am just curious about how I am supposed to believe that given that I am watching this on my iPhone 😅😅😅😅
This proves that Ricky Bobby's dad was correct. If you ain't first, you're last. Okay, which way to the door?
Why not both gates!!!
intel could have saved Scarlett johansson
many such cases
I get it
gate first?
gate last?
gate all around?
based monetization strat makes me want to subscribe but not rn lol
You said aluminum instead of aluminum...
28nm is the oldest node still viable for modern gaming and general consumer use. Where it fails in consumer CPUs is in things like modern video encoding, everything else, still can do, and probably could still be made to do. And it's been what, 13 years?
Your NMOS and PMOS illustrations are flipped FYI
It would have been hilarious if you had said "by the Asianometry patreon, early access members get to see videos first...or last."
Sorry, sorry, I'll see myself out.
I love how you pronounce aluminium the civilised way but semiconductor the Yankee way
And DRAM like a Klingon.
Video.
Can you cover intels raptor lake shitting the bed?
Mofet 😂
MOS stands for Metal Oxide SILICON! - Not 'Semiconducter"! Silicon being the substrate, ie, the chip itself.
No it is Metal-Oxide-Semiconductor. It's suppose to refer to the material stackup when taking a cross section of the transistor at the midline, which is right through the gate, oxide, and body of the transistor where the channel forms during inversion.
you basically have a phd in solid state physics with all these transistor videos haha
Stock video may be fun and all,
but it's very distracting to what we're trying to learn.
Man, I hate over-used stock video.
You get what you pay for…
Jon throws in the humor for free…
😃
420 views when I clicked to watch… nice… 😂
420? 😂
npn or pnp? or p**p
Now Intel is busy blowing out the ring bus in their own processors.
hi
So why is AMD dominating now? And is that related to Intel's huge issues with its most recent chips?
Hey why you do a video on where the $$$ is made.
Aluminum. Not aluminium. Stop this nonsense
We will spill blood over this
You are 80IQ