How To Improve Your PCB Layout - Power Planes
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- Опубліковано 21 жов 2020
- Commenting on a PCB Layout done by a junior engineer + some tips for power plane layout.
Links:
- How To Improve Your PCB Layout - VIAs: • How To Improve Your PC...
- How To Improve Your PCB Layout - Routing & Space: • How To Improve Your PC...
- PCB Manufacturing - Important facts you should know: • PCB Manufacturing - Im...
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As a junior engineer, your videos are incredibly useful
Thank you very much Abraxas
@@RobertFeranec It would be really really really great to have a summar of the main points in the description, and marks on the video time line. Or should I make them as I am watching this video? I have seen 8h of videos on topics related to PCB design and really need to make notes.
Robert , Copper between component lead , sometime I do have sometime I don't as depends on cases and design as follow :
1- component are too small less then 0603 , then no copper between leads
2- if component are bigger 0603 and I have copper pour and this plane is GND and one side of component is grounded, then I make more clearance to other pins , then copper pour between legs if I want keeps the ground plane as intact as possible , the more hole on plane the worse it get it from ideal plane GND
3- in case if the voltage is high, for example 35v rail voltage , then no copper between SMD part.
4- if I want hand solder parts then no copper
5- if I have design for voltage and current microvolt , like sensitives OP-amp with lowest leakage then no copper
6- high frequency , no copper but some time yes depends in size and situation,, high frequency return current get more complicated
well the list is long , I teach my self during past 40 years !
So nice explanation Paul. Thank you so much!
Could you explain the reasoning behind point 5 and 6? I was taught that as long as you don't have ungrounded or unconnected (islanded) copper pour it was okay, but is this not true at higher frequencies?
Others have mentioned etching problems as justification for not having 90 degree internal (concave) corners on a polygon, so I won't repeat that one again, but I couldn't see anyone mentioning 90 degree external (convex) corners. In high voltage (kV range) circuits any sharp edges - especially convex ones - tend to "compress" the electric field at the tip of the corner, making arcs from that location more likely. But as far as I can tell there are no issues with using them on low voltage boards, regardless of frequency.
I heard that modern etching techniques mostly eliminate issues with tight corners.
It feels like one of those things where you could ask 5 people and get 5 answers.
@@TomStorey96 :)
I avoid using 90 degree corners in polygons under the justification of too much charge concentrating in the edges, wich may cause noise/emission headaches. But I bias to agree with you about this effect being close to irrelevant under low voltages... it's only a good pratice that I have and follow, specially when I need to worry about energy/emission certification tests.
you are correct but it is seen as good practice
28:30 Another good reason to use larger clearance between copper and NPTH is drill location accuracy.
Drawing tracks for power before splitting up the plane fully - what an EXCELLENT strategy!
I'm starting with PCB design and I'm doing some audio projects on 2 sided boards. When I do that, it is important to use ground plane between signals to keep the crosstalk etc in check, especially since I don't have ground plane on top of that like you have in multilayer PCB. At least that's what I learned.
@ 19:37...Believe that the two branches of current floating around the opening in the PP will induce opposite directed mag. field thus resulting in no/a very small mag. field. I think you should be more concerned with not breaking a return path (if any) at the bottom of the PCB ... this could make a huge current loop to force this return current around the cutout. Conclusion .. I would keep the first layout
Thank you for making these “improve your design” videos. Always looking forward to them. I would like to see some videos about which components should I ideally keep apart from each other.
Thank you very much Joosep
Hi Robert, thank you very much for this insightful video. There are so many things in there that are helpful to show how to improve routing power. What I have liked about this series too, it that you show that with all your experience you are learning still. That there are things we have learned as 'this is how you do it' in the past, but that we now begin to understand that maybe it wasn't the best way, or that for modern high-speed circuits they are no longer good enough.
Thanks for showing us that tip of a keep-out for specific vias in a power plane. Specifically the 'reference voltage' for the SMPS chip. It may be easier to spot on a 4-layer board, but this will help a lot on any board to make sure the SMPS chip gets a clean reference and it will not connect through the polygon too.
Re: copper under components like capacitors and resistors: I try to avoid that. But I don't really know why. I just have. (Only on a 2-layer board I may do it. But only if I cannot have a solid ground layer on the bottom and under that component.)
A question: at 36:48 you show us how the memory signals need a reference to GND on both sides of L8. However, the GND polygon on the power layer L7 is also under parts of nearby tracks on all 4 corners. Doesn't that mean that those tracks (for example the differential pair on the lower-right side) now have a discontinuity in their reference? They do 'cross a gap' on the reference plane L7. One moment they have GND on both sides (L9 and L7), the next there is only GND on L9. I thought that would likely to change their impedance too? I don't have experience, but I think I would've redrawn the GND polygon on L7 to be only under the memory tracks. What do you think?
Thank you very much Christe4N. I keep learning a LOT when I am creating these videos ... and finally I also understand some of the recommendations :) I am very happy, that some other people see it the same way and find the videos useful. About the GND plane. I am not worried about the other signals, they are not very important and the L9 GND is much closer then L7, so it will have much bigger effect on the signals.
This video and all these comments... They're like a treasure.
I find your latest videos amazing. Thank you very much for your work!!!!
Thank you very much Victor
I actually use quite a lot of keep-out areas around certain sections. In the example shown here, the bunch of holes all the way on the left.
There is a lot of copper between the holes that is so small that it barely does anything, yet can be a potential problem for short-circuits.
It also helps on boards when you have to deal with high voltages (> 70V or even mains)
Thank You Robert. Much informative!!
Thanks Robert - another great video.
Layer Stack Manager - when modifying the Pullback Distance be certain to UNCHECK the Stack Symmetry checkbox, otherwise it will modify the 'other' symmetrical layer also [often a Ground layer].
Thank you Peter. You are right!
Excellent video, Robert!! Thank you!
Thank you very much guillep2k
Hi Robert, thanks for sharing the video
Great lesson Robert. I do not use polygon cooper between components because once had a short circuit problem ages ago and from there on never again.
Thank you Edgar for your feedback (and confirming my theory about possible short circuits)
What I missing in this video is... (But maybe it was mentioned in a previous one.)
Remove unused via pads in inside layers. After a Repour it can improve the polygons.
The PCB manufacturer will remove it anyway but they will not increase the polygon. So better if you control the situation.
Thanks for the videos!
Thank you Zoltan. Very good point. I do this through adjusting clearance rules for polygons. For a long time, Altium didn't have a direct support for this feature.
@@RobertFeranec This function has to be in since a long time at "Tools > Remove Unused Pad Shapes...".
This board has a lot of vias creating a lot of cheese in the Split Planes. I'd recommend doing the "Remove Unused Copper" feature for a good portion of the vias creating too much cut-out in the split planes; especially the vias that are grouped closer together not allowing copper to travel in-between.
In KICAD fill areas can be automated to apply radioused corners to avoid generation of sharp corners in the fill.
Nice!
Wow. Great content and video is very well done. Thanks so much for taking the time of sharing your experience and asking great questions.
Thank you Cedric
Thank you master.
Thank you very much for the great video Robert,
Very usefull and very informative.
Thank you very much Kerem
Thanks!
if the unused vias or unused pads(THT) break the plane, we can use the tool(remove unused pad shapes ) in Altium to eliminate the Annular Ring of thoses unused vias or unused Pads. The problem of the Breaking the plane will be mostly be solved. you can set the rules to minimize the distance between the poly and unused vias. But too close is also more risky
Hi Robert, thanks for all your great suggestions which where very interesting and to the point!!
It is always really helpful to have a visual example when discussing and explaining tips like these here!
Thank you very much giannis PS: Did you know, that youtube is showing you as one of my top commenters? :) Thank you for all your comments and feedbacks.
@@RobertFeranec Really? Didn't know that!
I think you have created some kind of community which is great! and I also really like your videos, I'm a fun! :) so I like leaving comments in order to show that and hope that helps and motivates you to keep up!
@@giannisasp1208 Thank you very much. I asked Marcela to contact you, so we can send you a T-Shirt :)
@@RobertFeranec She did contact me :)
Thanks Robert for the nice gesture!
Amazing Content, Your videos are Always useful. This channel should be recommended by UA-cam, if all engineering students knows this channel they Learn lot of things in Electronics Design. your way of Explaining is very clear and understandable for everyone , This channel deserves more. thank you sir
Thank you very much Haribabu
I really really like this! thank you Robert
Thank you very much Hung
In case of high speed signals that have small value series resistors, copper under the component matters. This can cause impedance discontinuity due to change of reference plane. It's all about the return current.
Thank you jarvenpaa
Why is the signal referenced to the plane that's on the same layer?
@@urmok6iv the signal goes through the resistor that is on top of the top layer.
How i see it, is that signal is always capacitively coupled to its surrounding conductors, as long as they are not galvanically isolated, which is rarely the case in PCBs.
@@jarvenpaajani8105 ok. Got it. If there is continuous copper under the signal then as the signal goes through the resistor it changes to the copper that's under the resistor.
Interesting, but if the reference path for the high speed signal is coupled to the immediate layer below the signal, I would expect the small amount of copper under the part would have an almost negligible effect. That is, unless you have a via under the part or very close. Either way, it’s still going to have a small impedance “bump”.
Hi Robert, Great work, and thanks for sharing your knowledge. @11.57, On copper between components, I usually would like to use more copper for power because if I use 1206, 0805 caps at buck output, I would want to use that space for more copper, I haven't so far seen any issues, polygon to polygon spacing I keep 15 mils. @16.04, I would also connect the feedback signal using a trace (15-20 mil wider) instead of the polygon as it's a very sensitive signal. Also @21.51 on 20H rule, most of the time I don't do in our boards and may be we certify the products for FCC and not individual boards and hence it might be just fine.
Thank you very much Chethan for a very good feedback.
I don't like to leave copper areas under smd capacitors, resistors etc.. Main reason, as You mentioned, to prevent short circuit and second one - parasitic capacitance.. Usually, in project settings I put in default clearance and other stuff and later I just update some net settings to make bigger clearance etc.. This helps me find errors from my side too.. For default settings, usually, best source is pcb manufacturers site. If I plan to make prototype PCB by my self, I already known what is possible and enter my own default data.. :D
About corners - I don't like to use square corners in tracks because this may result in fault point when etching the board.. I don't known how manufacturers deal with this, but if board is created at home, square corners in tracks are bad idea..
Thank you very much Arturs for your feedback.
Great, like always. still learning and getting stuck in 2 layers PCB. Hope one day get enough pro :D to leave a good comment!
When I started with designs I only placed tracks under 1206 resistors, never capacitors. Now I am placing vias, that are connected to on one of 0603 components in more compact designs. If it is a noisy component then it is better to have ground under. If it blocks noise (capacitors on the DC-DC) wider track with lower impedance is much better even if it extends under the component. Keep high impedance away from noisy nets, not just components.
Components are normally isolated, so you have to have a scratch on the mask and a damaged component (unless it is a flip chip). I never had a problem with copper under component. But I had a lot of problems with manufacturers making shorts even when using 0,4mm clearance for polygon pours :-/ . So make it as much clearance as possible as said in the video.
Thank you WR3 for your feedback. Very interesting.
your know sir...?
you make my life.....Easy and Professional...my dream is , i want to meet you and give you a big hug...
Great video!
Thank you Santi
Great content!
Thank you very much Jerome
Thank you so much Robert, I like you very much :)
Opinions about ninety-degree angles on polygon cutouts vary, of course. But once I saw a burnt inside corner of such a polygon. It was a polygon connecting a capacitor bank of a resonant converter where currents of more than 200 A flowed. And it was the inner coals that burned. Since then, personally, I always try to make cut corners or even round them. Well, the topic of outer corners still remains, although for high-voltage applications I still cut such corners because these are the ones that most often spark. On the other hand, none of this matters for boards with low voltages and currents, except for the return currents that all together want to go right through close corner.
Wow. Thank you Vasyl!
Another great video, Robert. Could any of your additional clearance rules be found under the "Advanced" tab, or do they all need to be custom?
Do you like to put stitching vias at the edge around the whole perimeter of the board that connects to GND?
Are thermal relief pads necessary when connecting eg SMD capacitors to a polygon?
NICE...!! Thanks!!
Thank you very much Santiago
Thank you Robert.
Unfortunately, the presentation you have pointed from Eric is only accessible for attendees on Altium Live.
Is it possible to resume or to give the reason why we should not pour GND over signal layers ?
Many Thanks
Great video, thanks. Can you do simpler boards that would apply to more people
15:21. I've had to use copper under components in scenario like the one you showed with a line of caps. The board was quite dense and i did not have a lot of space for the wide copper pour i really needed for the currents. When i added the copper under the caps i managed to get more current carrying capacity in the same area on the board. I'm talking about big 1210 caps. For smaller once i try to do this. For smaller caps ( 1206 and 0805, not 0603) i sometimes put the via (lets say GND via) under the cap in order to save space. I've never had any problems during manufacturing with board made that way.
Thank you very much Nik for your feedback.
@@RobertFeranec Hi Robert i have 1 more example where i've used tracks under components with great results. Picture of the layout -drive.google.com/file/d/1rVLjZPNkH8nWJSPMcfDy1m_5SMDzE7l9/view?usp=sharing . This is a DC-DC converter based on TPS562201DDCT (i use it for lighter loads than the nominal 2A). C20 is the input bypass cap (C19 is N.F.). By positioning it like this, between pins 1 and 3, with the SW track between the cap, i get very short current loops. The datasheet recommends for the SW track to be routed on another layer via vias, but that increases the current loop area. I've used that design many times and its always worked well. We assemble our boards in house, so whenever we have problems with assembly i know about them. This has never caused problems. Let me say it like that - you route vias and tracks under BGAs all of the time, if you had problems, you would have known.
PS - I know that my SW track has a net antenna and that will increase radiation, but this board will run at extreme temperatures and i wanna make sure that inductor is cooled off.
Hey great video! I learn alot from you!!
Can you make a video about power architecture?
I'm trying to find the app note that discusses a bit about copper placement under components. This one SCAA082A recommends removing copper under component when passive is of series/shunt termination resistor (more of a void of all layers). I can't find my other app note, but for decoupling caps and large switching areas, they recommended pulling copper as much as possible under the passives to minimize inductance. This would be your caps and inductors for switchers for example.
Thank you very much Filipe. Interesting.
If you don't have the space to adhere to the 20-H rule, you can run the plane much closer to the edge and get your PCB manufacturer to add edge plating. It's more expensive but it's very effective at reducing coplanar EMI problems. I've also seen people apply thin ground plane borders on their power plane layers, with via stitching, but I don't know how effective this is in practice.
For EMC regarding radiation, the via stitching should be the most effective solution. Depends on frequency spectrum of noise in power/ground.
The higher the critical frequencies the less distance between vias should be used (
@@icestormfr My understanding is that the plating is split rather than one complete ring. I've only ever seen it done on rectangular boards, though, so I'm unsure how they handle other shapes.
@@gsuberland i didn't mean the plating but the stitching vias with ground sourrounding the power polygon
@@icestormfr Ah, that makes sense!
Thank you, interesting discussion here
Very nice video!!! I want to know how you are introducing gaps between different islands on the power planes? Are you drawing each island manually or some kind of options are there in Altium such that islands are created with some specific gap in between them.
Once again, the good content video. I have a doubt regarding the PCB Impedance control. For example , I came to know that for Motor control PCB'S to measure the current they use the PCB impedance instead of current shunt resistor. But, I don't know how do they actually doing. If you know any details regarding the same , please share it.
Hi Robert!
Great video as always
I designed a board for the contactor, it has Modbus RS485, CANBUS, and ethernet inside, and a voltage of 220V enters the board. can you please help me find out How many layers you think the PCB should have and how should I arrange it?
On the topic of pouring ground on signal layers. I have been listening to Rick Harley presentations (he was also presenting at Altium Live 2020) and he makes a strong case for doing these ground pours. His major argument is that it helps to balance the copper on a particular layer if that layer is an outside layer during an electroplating operation. He said that if your copper is not balanced on those layers, the plating will not be evenly spread across the board. I believe he also makes the case that on two layer boards you will likely need to provide a ground return next to each signal (to avoid crosstalk, since the ground on the bottom is too far away). It seems like pouring the ground on these signal layers is a good way of providing this return (as long as it runs the entire length of the signal).
However, Bogatin and others say that ground pours form cavities that can resonate; I guess it depends on the engineering tradeoff between manufacturability and EMC.
@@anameisrequired3729 IDK, the only negative/downside I see for pouring ground on signal layers, especially with boards with a high number of IC's and components, is that you want to make sure that even though the pins might be connected to the GND pour, they should have GND vias close-by to shorten the return path to the reference plane underneath.
I think I answered similar comment somewhere here - I believe, if you need to balance copper, you may want to use small pieces of copper instead. I think, it is visible somewhere in this video: ua-cam.com/video/f6_svRNJYls/v-deo.html
I generally leave copper under components for 0402 components. If we are going to 0201, maybe you want to remove the copper to prevent shorting. A major point of concern is the PCB size, for very small PCBs you may need the copper under the components.
Thank you mztrmikachu
Good to know. I've been removing copper under most of my passives just out of paranoia (I tend to use cheaper board manufacturers) but I think I'll leave them in on my next prototype and see how it goes. I can definitely see a benefit to having a ground plane under there for better referencing.
@@gsuberland I typically use PCBWay and haven't had any problems at all, so you should be good!
ACcording to feedbacks of PMIC, 0Ohm res can be used for be more clear on Routing?
Hi Robert!
Great video as always :)
I have some thoughts in reference to 38:15
Long time ago I have read somewhere that it is possible that the pcb layers could collapse if they are not supported well. It happens when You are not using polygons in inner (signal) layers on relatively big ares. The polygons on signal layers are supporting the pressure of upper layers (and mounted components). If the upper layer collapse down to the lower one, the mechanical stackup dimensions could change and as a result the impedance (in this collapsed region) could also change.
Thank you Marcin. This is one of the things what Eric is talking about in his video. If it is needed, copper can be added - but it has to be broken into small pieces. It is also visible in my PCB manufacturing video here: ua-cam.com/video/f6_svRNJYls/v-deo.html
Please tell me what are the mathematical calculations behind the track selection. All video is good.
It is very useful for better understanding of how to implement power and gnd polygons in PCB.But I want to know reason why can't use gnd plane in signal layer? We need it in 50E impedance matching antenna track using coplanar waveguide for ground shield.
Very informative videos
thanks for making these kind of videos
i am new to PCB Designing so i wanted to know that what will be good books on PCB Routing Guidelines .
really helpful video.
Thank you very much Shubham
Hi! I just discovered your awesome videos. It is exactly what I was searching for so long time ago! I will watch all of them. If you have one or two books to advise, which one would be?
Thanks again for these tips, they are treasures! 😃
Thank you very much Tony. PS: There is a post on our forum about books: designhelp.fedevel.com/forum/test/other-aa/13002-books-for-the-developer Hope this helps.
Very good video!
I'd say that the copper under an MLCC isn't very likely to pick-up any noise, the parasitic capacitance between the MLCC and the copper underneath is probably negigible, and the surface area is too small to act as an antenna. Your concern about shortcircuit due to mechanical stress is more valid int hat case. Also, if the components needed any kind of glue underneath for SMT assembly, having no copper underneath leaves more room for it and avoids height concerns.
Thank you Francesc
Absolutely right!
Good day, your video is well explain... as im new about design pcb... i would like know if the following stack up its good for my project GND-Signals-Signals-GND and how proper use a ground planes for high speed traces like SPI bus
Question: Should we stop the flow between all small SMT components including capacitors, resistors, and inductors? It seems this would add parasitic capacitance every time or increase the capacitance of the desired capacitor beyond the value we wish. Thank you.
hello,
at 12:55about coppper under components, l used polyon cutoff to prevent copper creation under item especelially big Ind.
What you think about my technic?.
Pouring copper under the components... I think it depends on the size of the component... If you have enough cleareance, and no noise in the plane it can work, but if you can avoid it, just don't pour copper under...
"If you don't know what are you doing, just don't do it", nice recomendation haha
On AltiumLive Rick Hartley said that pouring ground copper around signal layers could help to contain fields... or even ground vias... Putting ground around signals: can it increase the capacitance of the line and cause signal integrity issues?
Nice video as always, Robert Feranec from FEDEVEL academy!
Thank you very much Juan
Great video Robert!
It would be of great help if you can upload a sample design rules file in your blog. It can help beginners like me to make use of different filters.
Thank you Bhagath. You can find a lot of rules in our open source projects (that is what I normally do, I just open a past project). You can download them here: www.imx6rex.com/
38:41 I am so confused right now. Rick Hartley suggest pouring a power plain between signals in his suggested 4 layers stack up: Ground--Signal/Power----Signal/Power--Ground
Hi Robert, This video is very very useful for my design. But I want to know which type layer is good plane or signal on layer stack up. What is the difference between two type . I thinking use signal layer stackup for all layer. What do you think about this situation.
Hi Robert, Thank you for the video! I have experimented with your suggestion of using tracks to connect the power initially (before I create the pours). However, one of the issues I have found with that approach is that as I am adding new signal vias, the vias collide with those tracks on the internal layers causing violations. You also have to be careful that the via doesn't pick up the name of the power net instead of the signal you are trying to provide a via for. If it was just a pour, the pour would just pour around the new via. Do you have a suggestion to minimize this artifact?
Another related question, do you always remove the tracks after you pour the polygons? They generally are enclosed by the polygon. Are there pros/cons for leaving them or removing them?
I usually connect powers at the end, so I do not really bump into tracks too much. I usually delete the tracks when polygon is used and before finishing the PCB. PS: Everything has advantages and disadvantages e.g. automatic repouring can be very annoying for bigger boards as it can slows down Altium a lot.
Robert, my $0.02
1) 90 degrees corners just ugly, from aesthetics point of view :)
2) One of PCB manufacturers points me to the fact, that insulation characteristics of PCB mask can't be assumed constant or just "good enough". So, keepout under SMD components is a good thing.
just last week i had a board come back from assembly where pullback for the planes got lost in some last minute changes and one of the boards apparently got bumped on its edge in assembly resulting in visible damage and planes almost shorting, maybe i will apply some paint or epoxy to small edge region without pullback but i certainly will pay attention to appropriate pullback in the future
This is a very nice feedback Tim. thank you!
What software we can use to convert .brd boardview to .tvw or .fz or .gr format boardview?
I can see that the Altium Designer can some sort of internal language to specify design rules to give full control. What is the best resource to learn this language?
The syntax itself looks as if it is Visual Basic.
Another awesome video Robert! Maybe this question was asked before somewhere but are there any plans to make this board be part of a future design course?
Thank you Bradley. PS: I have approval to use some parts of the board in some courses (e.g. maybe for DDR4 layout practicing?), but the complete layout can't be available.
Robert is king of pcb design 🤗😊
Thank you Pravin :)
Regarding copper filling over solder pads (as shown for the GND plane at 4:13). I have learned that from a solderability point of view, don't use solid copper pour over solder pads. Is this wrong (through hole and/or SMD)?
We have not had any problems / complains from assembly house about this, so we still keep using direct connection. However, I am aware of this topic and I was already thinking about if to change it or not.
At 34:50, you are showing the Saturn PCB Design Inc PCB toolkit to calculate how much current the PCB plane can carry. Why can't Altium do this internally?
as of problem on 17 minute. would this be more reliable to place "fake" component in schematic? which results in just two pads together, etc. It will connect feedback to power. this will create new NET. and then it could be much more reliable and efficient to enforce such rule.
Great video, it was very insightful!
For the 90 degree angles, in some cases, it's difficult to etch the copper out of a concave corner like that (same reason why you don't want 90 degree traces). It probably doesn't matter much for modern etching, but if the spacing is too small, then I have seen cases where there have been shorts (at least for home etching). Also, the 45 degree chamfers are much more visually pleasing.
A few questions:
- Is there a benefit to connecting power pins via traces or polygons on the footprint layer, or would you be better off not connecting the vias to the power plane? When you connect them on the footprint layer, you end up creating a small loop through the ventral axis of the PCB.
- For the component keepout, is that primarily for components involving the power planes? And is it only for polygon keepout? For example, would it apply to pull up resistors where you should avoid routing signals between the two pads (like for a staggered I2C pullups).
- In Altium, is there a reason why you used polygons for your power-plane only layers, rather than splitting a powerplane via a plane layer?
Thank you hjups PS: 1) about the copper in corner, yes, that is what I heard. 2) About Power pin connection on the footprint layer - in my mind, it may help to handle currents and lower impedance / inductance, but I have not really investigate deeper nor simulated, just my assumption. 3) generally I do not route under small components, especially if I use multiplayer PCB. I may route between pads in 1 or 2 layer pcb 4) It used to be hard to keep redoing shapes on plane layers (when an adjustment had to be done in plane layer with many powers), is it now easier?
@@RobertFeranec Thanks for responding.
I suspect that the loops for (2) will be too small to have an impact, though it would be interesting it if had an effect. I have been designing them unconnected though (since that's what most reference PCBs I have looked at do).
3) That's a good point, I guess there is no reason to route between them on a multi-layer board - it would save vias, but those are pretty much free.
4) I'm not sure if it's easier now, but I found it to be easy enough. You draw the dividing lines instead of the shapes, though it sometimes messes up the regions when you move the lines around. The benefit there though, is that in my experience, Altium has poor polygon manipulation tools, so you don't have to worry about polygon overlaps or extra vertices. Obviously it wouldn't work on a shared layer with signals though.
Robert, sometimes you tell about reference design. Is there a Altium link ?
Some of our Altium designs are published here: www.imx6rex.com/
As always Great Job, Thank you sir for such a newbie improver video.
May be removing copper under components make sense in terms of manufacturing risks, but what about inductors?
does keeping gnd copper under inductor helps for switching noise immunity?
Thank you Mustafa. PS: I almost always have GND as the second layer (usually just 75um / 3 mil under the layer 1)
Copper under non-shielded inductors for switching regulators or any high current application is counter productive, as part of the stray field induces eddy currents to the copper, which acts as a short, wasting power and reducing efficiency. You may even want to remove copper on several layers below such an inductor. For shielded inductors the stray fields get very low and just removing copper right under is more than enough.
@@LebrelZ very good point!
Is the reason for avoiding sharp corners on power planes to avoid creating unwanted antennas?
I don't generally remove copper under components but I do add polygon cutouts under specific noisy components or BGAs
Thank you for your feedback Brendan
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Hi, Robert. I have some questions about mounting holes for motherboards. It is non-plated but has mask-opened parts covered by tin around that non-plated hole (spots) which connected to GND and when we screw the bolt in to fix our motherboard in the case, the connection between board GND and rail (or shield) of the computer case will happen through this way: Board's GND polygon on the Top Layer-> Tin covered spots on the Top Layer -> the bolt which touches that spots by bearing surface -> case of the computer. I hope that I had explained my questions correctly)) Can you explain why non-plated holes with tin spots are used in a motherboard design? I assume that it just to exclude short circuits between inner layers and maybe provide more current flow through the bolt to the power supply instead of the direct way from Top Layer GND polygon.
Interesting, I have not seen this (or maybe I missed that). Now, I will keep checking mounting holes to see how many boards are designed like this. PS: I am not sure why they would do it that way.
The vias around the mounting holes are used to improve the rigidity of the board so that the screws do not squeeze the board when tightened.
One time, I saw rounded corners on ground and power plane. Is that better than 90 or 45 degrees angles?
Not principal. EMI almost radiates from spike corners. 45 (really 135) degree corners dont radiate EMI.
You mentioned using keepout areas under components to keep the polygon from flowing under it. Do you put the keepout area directly in the footprint or do you put it on the PCB directly? It seems like putting it in the footprint is better, but some people below have suggested that they only prevent the flow in certain situations depending on what nets are assigned to that particular component. In that case, it seems like you would want to put the keepout directly on the PCB or you would need to maintain two footprints in your library, one with and one without the keepout.
We added them into footprint .. and yes ... I have exactly the same dilema .. what about exceptions ....
I really like it, thank you. I have a suggestion, could it add subtitle? I am from China, my English is poor, but I really really like it
Thank you. PS: We are slowly adding subtitles to some videos.
Isn't it sufficient that we simulate the PCB and then we can be sure that there are no EMI issues?
So you mentioned using keep out areas to prevent copper between components, I guess you mean copper on the same layer or the adjacent layer. Is that correct? Did you get another expert professional opinion on whether that is good practice?
I don't get change the polygon colors and opacity. I want to see the tracks wich are over the polygon like in this video. Someone can help me?
How do I work with power planes in a dual layer board for example?
In two layer PCB you do not really have much options, usually there is not much space for power planes or big polygons. That is one of the reasons why 2 layer PCBs are not the best for many designs.
Can this PCB design be downloaded?
hi Robert, I'm no expert but
i did not get the point of removing the copper under components ... for short circuit .. if its already good clearance like 5-6mil and that copper plane will be covered with the solder mask? maybe for small footprints i would be afraid .. i've never did with 0603 or bigger .. ?
also i thought its good to couple the capacitor noise to the plane underneath it ? (at least to prevent radiation) ?
I see possible problems for example if mask opening is 0.1mm /4 mils and if minimum clearance is the same (or if mask is moved a little bit), then there may be places under the pads, what could be exposed and possibly create a short circuit PS: I usually use L2 as GND
@@RobertFeranec thank you for information very useful ill start editing all my small footprints 👣..
regarding the stack L2 gnd ..
i suppose top layer is closer to the component so stronger coupling and less radiation ?
So thats why i dont understand the noise point ..
Im discussing to learn ofc im less than junior level 😅
@@hasanalattar9561 I many of my designs, L2 GND is just 0.075mm under L1 ... so not so far away.
Hello Robert, can you give me the pcb and circuit diagram file in the video, I want to learn it, thank you.
I was told that 90 degree corners tend to radiate more at higher frequencies and that rounded corners are better than 45 degrees which are better than 90 degrees.
As for tracks under components, if the track is at 90 degrees to the component there should not be much cross-talk. However, anything less than 90 degrees will tend to couple.
Thank you again Robert. These videos are excellent.
Thank you Roger
I'm not a PCB professional, but it is not recommended to have copper near the inductor, as eddy currents will be induced in that copper which means more losses in the circuit.
To test that, simply measure a discrete inductor loss with/without a piece of copper on it like a copper tape, and you will see an increase in the losses i.e. dependent on some factors like the AC signal amplitude and frequency, core, shielding, airgap, inductor geometry.
So, simply remove the copper surrounding the inductor.
Youssef, very good point! (shielded vs non shielded inductors need to be also considered)
Robert, can you show how to watch video from Eric Bogatin you mentioned. When try to watch it I see the message: This recording is only available for specific ticket types.
Thank YOU!!!
Maybe we need to wait until they update the event website and post there the recording. It is possible to watch the videos from previous years, I guess, Altium will make public also these videos.
Not an electronics engineer. Interesting video :)
I like how any angle routing looks like. Almost looks like the 90s soviet Televisions used TopoR. Wonder how good at making a rough layout is an AI for component placing and routing. Surely for it to be any good it has to have schematics, proper component footprints, and quite some rules. Does it speed up a job?
Have seen boards with 90 degrees angled planes. Sharp angles should be avoided for easier etching.
Thank you ArthursHD. PS: I have not seen any super good autorouter yet. However I am also wondering when someone will come up with an AI autorouter and what the results will look like (as I know, there are no AI placement / routing tools yet ... if anyone knows something, please let me know)
@@RobertFeranec look at TopoR CAD - it autorouter generates pcb lines with no strict angles, - very brave try to improve EMI immunity.
Correct me if I'm wrong (and I haven't watched the whole video yet), but I see a lot of Ground-Loops (14:43 top-left of the View there is a Ground-Pad (2) which is connected to ground via two vias). Isn't that a ground-loop?
this is an interesting topic. we use multiple vias because of higher currents and impedance controlling, but I am collecting information about loops and if I find an expert for this topic, I will make a video and simulations.
@@RobertFeranec I use multiple vias all the time, but what caught my attention was they way you had connected them (a wire going to via-1, and a similar-size wire going from via-1 to via-2). If it was a larger copper island, maybe it would've not been the same (both inductance and capacitance would've looked different).
I think ground loops are only an issue if they have a large exposed loop area where they can pick up magnetic fields which induce currents; most likely the fear of ground loops is cargo cult of old high gain audio equipment?
Hi Robert, about your Altium config .
You have all tabs open with not minimize in group, where is this option??
I can't found how NOT minimize for example (9) files, you have all open files in visible tabs.
I can see you more PCB open in the 1:26min for example.
Thanks.
This will help (I was surprised, that more people noticed that:): designhelp.fedevel.com/forum/main-forum/altium/15789-document-tabs
@@RobertFeranec Thanks for reply Robert, i hope that too much people can see the comments, i was desesperate i couldn't found it ;)
Is there any benefit to using a plane layer instead of a polygon on a signal layer? I've found issues with via clearance on plane layers because I can't specify a clearance value for a net to another net on a plane layer. You can only specify all clearance for a single net.
I only use planes rarely in Altium. Advantage of using planes is for example, that polygons can show clearance error when you place or move VIAs and you need to keep polygons up to date (you have to keep refreshing them).
@@RobertFeranec Isn't that a good reason to use planes? I would fear to forget updating the polygons. Of caus. you need to check all your layers before creating production data. And you need to check the production data before submission. But my experience is that I have been working on details until last moment, and stress is an enemy.
@@MrJetra Altium has rules for modified polygons so if a DRC is the last process before generating output files then the modified polygons can be detected.
@@MrJetra I don't like polygons, I don't like planes because they are not easy to work with. However I prefer polygons, because it used to be a pain to work with plane layer. Is it now easier? - e.g. if you have a complicated power layer with many powers of different shapes, is it easy to adjust the shapes in plane layer? I have not tried that for a long long long time, maybe Altium improved that?
@@RobertFeranec I agree with you Robert. I have been using polygon pour instead of planes for at least 25 years.