Thank you Robert for getting to do these demonstrations with people like Eric and Rick! These videos are invaluable to anyone taking the time watching them. I've always known that there were issues with my PCBs, but I could never pinpoint where my designs failed me. Your videos have been a real eye-opener. If I could make a request for future content, it would be S-parameters with regards to Power Delivery Networks. It's all fine and well for designing your signal traces, but if your power delivery is not done correctly, as Eric says: You're screwed!
Picking up from the last couple of minutes of the video, I'd relly like some new video about connectors and cables; especially between boards. For example, I have a board I have to interface with that requires several connectors, which means several GND cables. What is the best way to avoid ground loops in that case, handle EMI, GND bounce, etc? A good in-depth video about this would be greately appreciated.
This method also works in the opposite direction. I made a few pipe organ control electronics, where hundreds of solenoids have to be wired to the outputs. I use a 10-pin ribbon cable for each 8 outputs, with two common positives. These pins are soldered to the common positive rail under the solenoids. Suppression diodes were mounted to the pcb. Conventional wiring uses a group cable for the OC outputs, and the common positive is connected directly to the PSU. If a lightning hit the tower of the church, with conventional wiring, at least a few mosfets die. With my wiring method, lots of my boards survived, when other equipment failed in the church. So the return path is also important protecting sensitive circuits against EMI issues.
I'm not affiliated in any way with Eric and I usually do not recommand books. But here I think people involved in PCB design can benefit from reading Eric's books. From his books you will learn how a PCB is component in itself and how this component you design will behave, taking some of the guesswork out of the process and focus on the important aspects. -Principles of Power Integrity for PDN Design--Simplified: Robust and Cost Effective Design for High Speed Digital Products -Signal and Power Integrity - Simplified
Excellent video as always!! I just want to point out that the noise you saw at the end, with the section of the board with the continuous GND plane at the bottom, happens because you have a huge separation between your signals in the top and the gnd plane at the bottom. We are talking about the whole board, or in other words 62mil thickness separation between the signals and their return paths, so that noise spike when switching the IO closer to the victim doesn't surprise me. If you were to decrease the separation from top to bottom from 62 mil to 4 mil then you would not see that noise.
Super nice video, Robert! Good on-point questions as always. Also, I like how you take the time to clarify some concepts, even if it is briefly; it helps for rounding up the ideas.
Sir thank you very much for this great video which I waiting for long time in this great youTube channel We need more videos with Eric , thanks for helping all through your videos sir
I look forward to that differential signal video! The issues I run into are always because of high speed differential signals. Single ended in my case is always slow enough they never have issues. Specifically above 6Gbaud
57:10 "The noise happens on the edges..even if the clock rate is only 1 MHz or 50 kHz...." A related strategy to reduce trouble is to control the switching speed, which reduces the magnitude of pulsed current demand. That could mean from software setting the "drive strength" of the I/O pins on an FPGA or SoC. Or when using glue logic chips (eg: from 74xx family) avoid using a family that is much faster than you need. And this topic of course overlaps with managing impedance of longer traces etc.
Robert -- Many thanks for your efforts, as always. However there were some key points the weren't clear to me. 1) What is the nature of the victiim line? Is it driven? How is it terminated? The scope shows noisy voltages appearing on it, but not knowing what that the victim line is connected to, that waveform is difficult to assess. 2) Though hard to see, is it safe to assume that both the scope probes have spring ground connectors? Are the scope probe grounds isolated from one another? 3) I'm assuming the victim line probe was measuring the victim signal line. So how is it revealing ground bounce specifically, which is surely by definition on the ground line, which would need to be measured relative to some non-bouncing reference? And even more puzzling is that when Eric moved from shared return to separate return, I didn't see him move the victim probe or its ground, so apparently it was still measuring the victim line referenced to the same ground as before. The video shows a series of compelling waveforms displaying real-life examples of phenomena that we know are important... but that only makes us more eager to know the accurate details!
Excellent video as usual, Eric really knows how to explain these subjects. You are forcing me to improve a couple of tracks in the board I'm currently routing.
wonderful video, robert! i really really enjoyed this one, even after a long day at work! such an interesting way of teaching stuff, i love watching eric's talks too! recently ordered his book and am looking forward to reading it :-) keep up the great work!
Thanks Robert. Super informative lecture. Thanks a lot Eric for creating an awesome training PCB. I could not help think that where ever possible, we need to keep the currents flowing in our signal lines as small as possible. I think that would reduce ground bounce and inductive coupling because lower currents will cause lower IR voltage in Ground plane and lower magnetic-fields. would you agree?
Oh my goodness, this reminds me of one of my own boards that didn't work because of exactly this reason. I had one of these FPGA breadboard modules (with a single ground pin!) and a signal going over a a long cable to my board and directly into the FPGA. The amount of ground bounce was so insane that the 5 MHz clock suddenly started to have ~5% more edges than intended! I eventually worked around this inserting a schmitt trigger buffer in the line and that luckily saved my new design (without changing the cable).
Single ground pin eh?! I'm guessing it's a Digilent Cmod A7. Kind of annoying. I resorted to physically cutting traces on the Cmod A7, to some unneeded I/O pins, and wiring those to ground, so the module would have several ground pins. You can also attach an additional ground to the PMod connector, though it's on the end.
@@Graham_Wideman Haha, almost on point. It was the predecessor Cmod S6. This didn't have the PMOD connector but I actually used the other unpopulated connector (I think it's JTAG) to get another ground pin. Not sure how much it actually helped to improve the situation since I tried multiple things to get rid of the grounding problem.
Try working around a Q-switched laser. The Q-switch often has 3KV in 15ns edges and they show up EVERYWHERE. Quickly teaches you to up your EMI game. What's you thoughts on decoupling power wires at connectors so they act as "ground" for transmission lines in a cable?
Thanks for the interesting video! I wonder how realistic the setup is, because the victim line is a high impedance line (I'm guessing 10MOhm from the oscilloscope?). Would the result be any different if you for example switch your oscilloscope to 50 ohm?
Why is the noise around/after switching off so much higher than the noise around switching on? (Clear examples around 20:15 and in self-aggression at 22:30.) Are the rise times slightly longer than the fall times, and it matters hugely? Does ringing magnitude somehow scale to the final voltage level? Would it somehow matter if you were using negative voltage, or if you let it settle into an "on" state for a while before starting the traces?
Thank you so much ❤ I have learned alot from your videos. I just have question: In the second scenario(solid gnd under every signal), does reducing board thickness also reduce noise?
When I was editing the video and especially creating the thumbnail, I noticed, that maybe a different color could be more visible. If I do not forget, I will be more careful next time.
Hi robert, Can you post vedio on Mosfet driver based on fulbridge topology and High power PCB design. In which Mosfet are being driven on 110-220v. High current driving through pcb tracks.
Nice demonstration there. So for a two layer board one would have a solid ground on the bottom layer and signals on the top layer. But what about ground (or VCC) poor on the top layer? Will that reduce noise as well?
I do not normally do that. In some situations it may be hard to tell what would be happening on these pours and if done wrong, it could cause some problems.
Hi，Sir, I have a question about power / ground routing layout equivalent parasitic inductance. So how to estimate its value? It looks not like narrow signal routing layout estimated value , e.g. 0.5nH / mm
Is there any type of filtering required to reduce noise/ EMI/EMC. I have designed a microcontroller board based on atmega128A, it has many other IC's. its working perfectly. But little problem of Noise/EMI/EMC. it has a small AC motor operated through a relay. switching of motor sometimes freeze RTC and get garbage on LCD. Is it possible for you to review my PCB ?
Thanks for the great video. I have a question: in this and also some other videos it was stated that the highest frequency on the board is defined by the fastest rise time (RT) of a signal (and not the actual switching frequency). So how would you calculate the max frequency? Just 1/RT?
I don't see that 5V vs 3.3V make that much of a difference. Since your signal threhold is voltage dependent, and 30% of one or the other on peak noise voltage is going to be spectacularly dicey either way. Classic boards of the 80s with very adventurous routing were 1-2 MHz boards, not 20MHz. While the frequency per se isn't necessarily significant, the semiconductors also had much shallower slower flanks, which is i think why crosstalk wasn't that relevant. If you have a modern-ish 20MHz device running at 1MHz, it's not going to help you, you still have those steep flanks to deal with. But also they all had subsantial analogue issues such as video "jailbars" etc, these weren't clean devices.
I have working on some design that uses ADC. I am not able to get the stable adc reading of the potentiometer. The value fluctuate one to two point on Arduino and on other microcontroller. What might cause this issue and how can I eliminate this behaviour
Multiple factors can cause the response you are seeing, including but not limited to... 1. Pot's are physical contacts on a resistive element which will introduce noise, you can isolate this uncertainty by replacing the pot with a resistor divider. 2. ADC's have a parameter that states the "effective number of bits" that is basically telling you the noise floor of the ADC. Refer to the datasheet for this value. 3. Breadboards are notoriously noisy, not sure what you're using but consider designing a cheap PCB if your problems aren't addressed by the first two considerations I listed. 4. The type of ADC effects the performance and signal conditioning required, if the ADC has a high impedance source, RC snubber, input capacitance, ect... 5. Reference voltage of the ADC is noisy or sharing a common rail with core VCC. There are lots of sources of noise, such as those covered in this presentation, but it's not likely that you are having a single source causing the LSB errors. Aside from the hardware related solutions to reduce noise, you could implement a software solution to help stabilize ADC readings regardless of the noise at the expense of response time. Running average or oversampling of the ADC are common methods, these averaging methods will smooth the small variance in LSB noise and depending on the iterations of the averaging, can cause more problems than they fix depending on the application. In order to provide a more effective solution we would need to know more about the application, as the solution could be simple or demand a better ADC. For a better understanding of how you should buffer the signal take a look at some application notes for similar ADC's, it's never a simple pot directly connected to a ADC input. A typical low noise application would have the high impedance pot buffered, followed by a RC snubber and input capacitance based on the sampling frequency of the ADC.
Hi Robert, perhaps my request will be unpopular, however please could you make also shorter version and cut the video to perhaps 15minutes,? I usually don't have time to watch over hour long videos.
Hello Robert, please answer below qureies and clarify my confusions: At Test Point TP5, Is the Victim Signal line connected to the microcontroller IO pin or just an open pin with a purple Oscilloscope probe connected to it? Am I right assuming that the Victim line's return path connects to GND of the controller board in either way if we switch the jumper to common return or separate return path?
Thx Robert, Eric's contributions are always very precious. Ok, so as a general rule it's a good idea to have the return path under the signal which I often achieve by having a layer which is all GND. But very often in my projects I also have a plane/layer with large areas of VCC. Now, sometimes, due to crowd routing needs :) , I have to route a signal on the other side of the PCB where the internal GND area is shielded by the VCC area. Is this preventing the "effect" of the GND acting as return path ? Basically I have 4 layers: signals, GND, VCC, signals , are the signals on the bottom shielded (for what regards the current return path )from GND because of the VCC layer ?
I think so. I believe some designs add "stitching capacitors" between gnd/vcc near the points where the trace switches sides, to permit return signals to travel through vcc.
Fantastic video. I wish that it had shown up in my UA-cam feed. For some reason, the algorithm is filling my feed with political stuff that I have no interest in...
Very long video unfortunately, a summary would have been better as i cant seem to understand whats going on if i skip a part of it and watching all of it is too much
Thank you Robert for getting to do these demonstrations with people like Eric and Rick! These videos are invaluable to anyone taking the time watching them. I've always known that there were issues with my PCBs, but I could never pinpoint where my designs failed me. Your videos have been a real eye-opener.
If I could make a request for future content, it would be S-parameters with regards to Power Delivery Networks. It's all fine and well for designing your signal traces, but if your power delivery is not done correctly, as Eric says: You're screwed!
Thank you Robert! Talks with industry veterans are always so illuminating!
Picking up from the last couple of minutes of the video, I'd relly like some new video about connectors and cables; especially between boards. For example, I have a board I have to interface with that requires several connectors, which means several GND cables. What is the best way to avoid ground loops in that case, handle EMI, GND bounce, etc? A good in-depth video about this would be greately appreciated.
Thank you for video, interesting conversation. Greetings from Saint-Petetsburg, Russia. Respect for experienced engineers!
This method also works in the opposite direction. I made a few pipe organ control electronics, where hundreds of solenoids have to be wired to the outputs. I use a 10-pin ribbon cable for each 8 outputs, with two common positives. These pins are soldered to the common positive rail under the solenoids. Suppression diodes were mounted to the pcb. Conventional wiring uses a group cable for the OC outputs, and the common positive is connected directly to the PSU. If a lightning hit the tower of the church, with conventional wiring, at least a few mosfets die. With my wiring method, lots of my boards survived, when other equipment failed in the church. So the return path is also important protecting sensitive circuits against EMI issues.
Awesome demo! More Bogatin demos!
Man, I love this guy so much, I wish he was my professor. Please make more videos with him, his knowledge is invaluable.
I'm not affiliated in any way with Eric and I usually do not recommand books. But here I think people involved in PCB design can benefit from reading Eric's books. From his books you will learn how a PCB is component in itself and how this component you design will behave, taking some of the guesswork out of the process and focus on the important aspects.
-Principles of Power Integrity for PDN Design--Simplified: Robust and Cost Effective Design for High Speed Digital Products
-Signal and Power Integrity - Simplified
Thanks Robert and Eric
This was one of the best videos I've seen, full of wisdom!
searched for ground bounce and that is an awesome lesson, thank you
It is better 1 time to see than 100 times to read/hear theory about something :) Thank you for video with real experements.
Thank you Robert and thank you Eric.
My best spent hour in years ! Your channel is pure gold, keep it up Robert !
Excellent video as always!!
I just want to point out that the noise you saw at the end, with the section of the board with the continuous GND plane at the bottom, happens because you have a huge separation between your signals in the top and the gnd plane at the bottom. We are talking about the whole board, or in other words 62mil thickness separation between the signals and their return paths, so that noise spike when switching the IO closer to the victim doesn't surprise me. If you were to decrease the separation from top to bottom from 62 mil to 4 mil then you would not see that noise.
Great stuff, thanks! Seems this rabbit hole never ends.
This video is very informative for beginners, Thank You.
Excellent interview! Thanks.
Great video! Would be interesting to see the no ground plane version, but with a wider trace for the shared return path section.
already looking forward to diff signals :)
Me too :)
Thank you so much Eric and Robert!
Thank you for this informative video😍
Super nice video, Robert! Good on-point questions as always. Also, I like how you take the time to clarify some concepts, even if it is briefly; it helps for rounding up the ideas.
Thank you very much guillep2k
OOO, Eric!!! Collaboration of Robert and Eric, what could be better?!
Thanks, really helps to think about sylabus fom my students, nice example nice video.
Love from India..
This video is ocean of knowledge..
Sir thank you very much for this great video which I waiting for long time in this great youTube channel
We need more videos with Eric , thanks for helping all through your videos sir
Thank you very much Haribabu
great video, A lot more people on the tub's need to watch this.
Excellent video,Thank you!
I look forward to that differential signal video! The issues I run into are always because of high speed differential signals. Single ended in my case is always slow enough they never have issues.
Specifically above 6Gbaud
Smashing vid Rob. Well done!
57:10 "The noise happens on the edges..even if the clock rate is only 1 MHz or 50 kHz...." A related strategy to reduce trouble is to control the switching speed, which reduces the magnitude of pulsed current demand. That could mean from software setting the "drive strength" of the I/O pins on an FPGA or SoC. Or when using glue logic chips (eg: from 74xx family) avoid using a family that is much faster than you need. And this topic of course overlaps with managing impedance of longer traces etc.
Robert -- Many thanks for your efforts, as always. However there were some key points the weren't clear to me.
1) What is the nature of the victiim line? Is it driven? How is it terminated? The scope shows noisy voltages appearing on it, but not knowing what that the victim line is connected to, that waveform is difficult to assess.
2) Though hard to see, is it safe to assume that both the scope probes have spring ground connectors? Are the scope probe grounds isolated from one another?
3) I'm assuming the victim line probe was measuring the victim signal line. So how is it revealing ground bounce specifically, which is surely by definition on the ground line, which would need to be measured relative to some non-bouncing reference? And even more puzzling is that when Eric moved from shared return to separate return, I didn't see him move the victim probe or its ground, so apparently it was still measuring the victim line referenced to the same ground as before.
The video shows a series of compelling waveforms displaying real-life examples of phenomena that we know are important... but that only makes us more eager to know the accurate details!
Excellent video as usual, Eric really knows how to explain these subjects. You are forcing me to improve a couple of tracks in the board I'm currently routing.
Thank you Robert! Help a lot!
wonderful video, robert! i really really enjoyed this one, even after a long day at work! such an interesting way of teaching stuff, i love watching eric's talks too! recently ordered his book and am looking forward to reading it :-) keep up the great work!
This is one of my favorite channels. Thx Robert. Even though i m not working in RD anymore, i m still fancy about electronics. Super^_^
Excellent.
Thanks Robert. Super informative lecture. Thanks a lot Eric for creating an awesome training PCB.
I could not help think that where ever possible, we need to keep the currents flowing in our signal lines as small as possible. I think that would reduce ground bounce and inductive coupling because lower currents will cause lower IR voltage in Ground plane and lower magnetic-fields. would you agree?
Thank you so much!!!
Oh my goodness, this reminds me of one of my own boards that didn't work because of exactly this reason. I had one of these FPGA breadboard modules (with a single ground pin!) and a signal going over a a long cable to my board and directly into the FPGA. The amount of ground bounce was so insane that the 5 MHz clock suddenly started to have ~5% more edges than intended! I eventually worked around this inserting a schmitt trigger buffer in the line and that luckily saved my new design (without changing the cable).
Single ground pin eh?! I'm guessing it's a Digilent Cmod A7. Kind of annoying. I resorted to physically cutting traces on the Cmod A7, to some unneeded I/O pins, and wiring those to ground, so the module would have several ground pins. You can also attach an additional ground to the PMod connector, though it's on the end.
@@Graham_Wideman Haha, almost on point. It was the predecessor Cmod S6. This didn't have the PMOD connector but I actually used the other unpopulated connector (I think it's JTAG) to get another ground pin. Not sure how much it actually helped to improve the situation since I tried multiple things to get rid of the grounding problem.
Great video!
Thank you Santi
Try working around a Q-switched laser. The Q-switch often has 3KV in 15ns edges and they show up EVERYWHERE. Quickly teaches you to up your EMI game. What's you thoughts on decoupling power wires at connectors so they act as "ground" for transmission lines in a cable?
Always interesting and useful!
Thanks for the interesting video! I wonder how realistic the setup is, because the victim line is a high impedance line (I'm guessing 10MOhm from the oscilloscope?). Would the result be any different if you for example switch your oscilloscope to 50 ohm?
Exactly what I was thinking
Why is the noise around/after switching off so much higher than the noise around switching on? (Clear examples around 20:15 and in self-aggression at 22:30.) Are the rise times slightly longer than the fall times, and it matters hugely? Does ringing magnitude somehow scale to the final voltage level? Would it somehow matter if you were using negative voltage, or if you let it settle into an "on" state for a while before starting the traces?
Perfect.
Where is the ground connected on the scope probe?
Thank you so much ❤
I have learned alot from your videos.
I just have question: In the second scenario(solid gnd under every signal), does reducing board thickness also reduce noise?
thank you sir * * * * *
can we get the gerber of that pcb?? as it will help us to understand more.
Black background might look cool and gangsta but makes it difficult to see the red traces.
When I was editing the video and especially creating the thumbnail, I noticed, that maybe a different color could be more visible. If I do not forget, I will be more careful next time.
amazing video,
Hi robert, Can you post vedio on Mosfet driver based on fulbridge topology and High power PCB design. In which Mosfet are being driven on 110-220v. High current driving through pcb tracks.
summery?
Pls give as examples
Nice demonstration there. So for a two layer board one would have a solid ground on the bottom layer and signals on the top layer. But what about ground (or VCC) poor on the top layer? Will that reduce noise as well?
I do not normally do that. In some situations it may be hard to tell what would be happening on these pours and if done wrong, it could cause some problems.
Hi，Sir, I have a question about power / ground routing layout equivalent parasitic inductance. So how to estimate its value? It looks not like narrow signal routing layout estimated value , e.g. 0.5nH / mm
Is there any type of filtering required to reduce noise/ EMI/EMC. I have designed a microcontroller board based on atmega128A, it has many other IC's. its working perfectly. But little problem of Noise/EMI/EMC. it has a small AC motor operated through a relay. switching of motor sometimes freeze RTC and get garbage on LCD.
Is it possible for you to review my PCB ?
Thanks for the great video. I have a question: in this and also some other videos it was stated that the highest frequency on the board is defined by the fastest rise time (RT) of a signal (and not the actual switching frequency). So how would you calculate the max frequency? Just 1/RT?
1/2Rt because the signal has to rise and fall to complete a cycle. And use the fall time if that is shorter
26:40 Does that meam, if im not probing it there would be no ringing?
And if thats true, is there a way to avoid resonanz with my probe?
Could you please enable auto caption option?
They are enabled, they are just not often created ... I do not know why.
I don"t understand why changing the return path increase the inductance
I wish I could give more then 1 like
I don't see that 5V vs 3.3V make that much of a difference. Since your signal threhold is voltage dependent, and 30% of one or the other on peak noise voltage is going to be spectacularly dicey either way.
Classic boards of the 80s with very adventurous routing were 1-2 MHz boards, not 20MHz. While the frequency per se isn't necessarily significant, the semiconductors also had much shallower slower flanks, which is i think why crosstalk wasn't that relevant. If you have a modern-ish 20MHz device running at 1MHz, it's not going to help you, you still have those steep flanks to deal with. But also they all had subsantial analogue issues such as video "jailbars" etc, these weren't clean devices.
I have working on some design that uses ADC. I am not able to get the stable adc reading of the potentiometer. The value fluctuate one to two point on Arduino and on other microcontroller. What might cause this issue and how can I eliminate this behaviour
Multiple factors can cause the response you are seeing, including but not limited to...
1. Pot's are physical contacts on a resistive element which will introduce noise, you can isolate this uncertainty by replacing the pot with a resistor divider.
2. ADC's have a parameter that states the "effective number of bits" that is basically telling you the noise floor of the ADC. Refer to the datasheet for this value.
3. Breadboards are notoriously noisy, not sure what you're using but consider designing a cheap PCB if your problems aren't addressed by the first two considerations I listed.
4. The type of ADC effects the performance and signal conditioning required, if the ADC has a high impedance source, RC snubber, input capacitance, ect...
5. Reference voltage of the ADC is noisy or sharing a common rail with core VCC.
There are lots of sources of noise, such as those covered in this presentation, but it's not likely that you are having a single source causing the LSB errors.
Aside from the hardware related solutions to reduce noise, you could implement a software solution to help stabilize ADC readings regardless of the noise at the expense of response time. Running average or oversampling of the ADC are common methods, these averaging methods will smooth the small variance in LSB noise and depending on the iterations of the averaging, can cause more problems than they fix depending on the application. In order to provide a more effective solution we would need to know more about the application, as the solution could be simple or demand a better ADC. For a better understanding of how you should buffer the signal take a look at some application notes for similar ADC's, it's never a simple pot directly connected to a ADC input.
A typical low noise application would have the high impedance pot buffered, followed by a RC snubber and input capacitance based on the sampling frequency of the ADC.
👏👏
The Clock at Right that doesn't move ..lol
And I thought, no one will notice ;) PS: I often remove time as it may be disturbing when I cut the videos
Hi Robert, perhaps my request will be unpopular, however please could you make also shorter version and cut the video to perhaps 15minutes,? I usually don't have time to watch over hour long videos.
Best watched at 1.5x speed.(minimum)
He does not seem to have a common connection on the probe???????
He's using the tip-spring ground connection: electronics.stackexchange.com/questions/136123/how-do-you-attach-an-oscilloscope-ground-spring
Hello Robert, please answer below qureies and clarify my confusions:
At Test Point TP5, Is the Victim Signal line connected to the microcontroller IO pin or just an open pin with a purple Oscilloscope probe connected to it?
Am I right assuming that the Victim line's return path connects to GND of the controller board in either way if we switch the jumper to common return or separate return path?
Thx Robert, Eric's contributions are always very precious.
Ok, so as a general rule it's a good idea to have the return path under the signal which I often achieve by having a layer which is all GND.
But very often in my projects I also have a plane/layer with large areas of VCC.
Now, sometimes, due to crowd routing needs :) , I have to route a signal on the other side of the PCB where the internal GND area is shielded by the VCC area. Is this preventing the "effect" of the GND acting as return path ?
Basically I have 4 layers: signals, GND, VCC, signals , are the signals on the bottom shielded (for what regards the current return path )from GND because of the VCC layer ?
I think so. I believe some designs add "stitching capacitors" between gnd/vcc near the points where the trace switches sides, to permit return signals to travel through vcc.
Fantastic video. I wish that it had shown up in my UA-cam feed. For some reason, the algorithm is filling my feed with political stuff that I have no interest in...
Thank you ats89117 PS: Yes, UA-cam algorithm is not very friendly to educational videos :(
Your content would be very interesting but listening to you is a pain.
Very long video unfortunately, a summary would have been better as i cant seem to understand whats going on if i skip a part of it and watching all of it is too much