Hi Tom, it will be very helpful if you give some more context. Please tell about the existing project, its ports that will finally map to FPGA I/O pins, wires which will not map to FPGA I/O pins but we wish to monitor them, then show the generated ports and logic after implementation at different steps etc. Then show some test cases of it triggering, may be with or without an actual oscilloscope. This is way too fast and misses a lot of details that are very relevant to the context of when and how to use to get some results. Q - What happens after I insert the IP and implement and see a fault ? Is the further debugging only using an oscilloscope ? Thanks.
All of your comments are right on. Thank you. I was trying to keep this one short. I agree that there needs to be a longer one using the newer versions of vivado.
Great, thanks. I've used the other method of having Vivado insert an ILA after synthesis. There's a "wizard" for. One thing I also struggled with today was lowering the speed of the clock that takes samples once the trigger condition is met. Most of my system runs on a 50Mhz clock, but one module generates a pattern that takes 40ms to finish. At 50Mhz, there isn't enough capture memory to get the entire thing. I tried enabling a 1 Mhz clock and making the ILA use that, but I got into all sorts of trouble.
mdesm2005: Hey, since I also had all kinds of trouble (mainly with user chain settings), I read quite a lot about troubleshooting ILAs. You need to make sure that your active input clock for the ILA still has a frequency at least twice as high as the JTAG frequency of your device. You can simply lower the JTAG frequency in Hardware Manager if you have a "slow" input clock to your ILA. Cheers, Tim!
sir , what i the exact difference between trigger out port and trigger in port, if perticular pin in FPGA used as in put from other slave or field then how should I treate that signal ( either in or out port), at the same time if perticular pin is used as inout in my project if I want to monitor how should I treat that in Debugging ports. Please suggest me. Thank you very much sir,
Hi Tom, thanks for the informative video. Is there a way of getting the $counter0 value using the advanced mode script. I am trying to count transitions on a signal and vivado waveform viewer does not have this option.
want to learn how to design Xilinx FPGAs? join today to my Udemy course on this link: www.udemy.com/course/vivado-learn-from-the-beginning-and-with-pcie-full-project/?referralCode=35850E883A41A0FCECE8
Great video - but please silence the keyboard ... when you start typing you can hear nothing else :)
Extremely helpful, thank you for your time
Hi Tom, it will be very helpful if you give some more context. Please tell about the existing project, its ports that will finally map to FPGA I/O pins, wires which will not map to FPGA I/O pins but we wish to monitor them, then show the generated ports and logic after implementation at different steps etc. Then show some test cases of it triggering, may be with or without an actual oscilloscope. This is way too fast and misses a lot of details that are very relevant to the context of when and how to use to get some results. Q - What happens after I insert the IP and implement and see a fault ? Is the further debugging only using an oscilloscope ? Thanks.
All of your comments are right on. Thank you. I was trying to keep this one short. I agree that there needs to be a longer one using the newer versions of vivado.
Why didn't you use a 4K screen? The screen is so crowded.
Great, thanks. I've used the other method of having Vivado insert an ILA after synthesis. There's a "wizard" for. One thing I also struggled with today was lowering the speed of the clock that takes samples once the trigger condition is met. Most of my system runs on a 50Mhz clock, but one module generates a pattern that takes 40ms to finish. At 50Mhz, there isn't enough capture memory to get the entire thing. I tried enabling a 1 Mhz clock and making the ILA use that, but I got into all sorts of trouble.
mdesm2005:
Hey, since I also had all kinds of trouble (mainly with user chain settings), I read quite a lot about troubleshooting ILAs.
You need to make sure that your active input clock for the ILA still has a frequency at least twice as high as the JTAG frequency of your device.
You can simply lower the JTAG frequency in Hardware Manager if you have a "slow" input clock to your ILA.
Cheers, Tim!
Too much focus buried in his screwing around with his logic and little time talking about the features of the tool.
Excellent thank you! I'm using Vivado 2021.2 with a Zedboard.
sir , what i the exact difference between trigger out port and trigger in port, if perticular pin in FPGA used as in put from other slave or field then how should I treate that signal ( either in or out port), at the same time if perticular pin is used as inout in my project if I want to monitor how should I treat that in Debugging ports.
Please suggest me.
Thank you very much sir,
Hi Tom Thank you , Where can I access this code
Hello sir, can you make some videos on zynq 7000 soc
Excellent demo of the ILA debugger. Thank you.
Can we trigger input signals to fpga.
Sir i want a video on vio please
Sir i want trigger in example
Hi Tom, thanks for the informative video. Is there a way of getting the $counter0 value using the advanced mode script. I am trying to count transitions on a signal and vivado waveform viewer does not have this option.
want to learn how to design Xilinx FPGAs? join today to my Udemy course on this link: www.udemy.com/course/vivado-learn-from-the-beginning-and-with-pcie-full-project/?referralCode=35850E883A41A0FCECE8
Very good，And can you tell me what video recording software is？
Camtesia
Does the diligent board come with a license to use Vivado?
U can use vivado webpack edition for free
very good
Great Job
This is OLD, take this video down! Use the wizard and save tons of time and do not modify your source code!
How do you do it?