Plot IDS vs VDS for the circuit : Interview question for "Analog Circuit Design in a MNC"

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  • Опубліковано 20 вер 2024
  • In this video we will solve the question without using equations.
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КОМЕНТАРІ • 13

  • @vlsiorg
    @vlsiorg  2 роки тому +3

    Correction to the last part of the graph :
    For VX > 1V , Vx will be the drain , So VGS will be 1V and the mos will be on . Under this condition , for VX >=1V MOS will be in saturation.
    *For VX=1V IX=0 , VDS=0 here.
    *For VX < 1V , Vx wil be the source , under this condition , as rightly pointed out by you, we are at the edge of saturation. So for VX

  • @vlsiorg
    @vlsiorg  2 роки тому

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  • @praveenkumarmaddeti6668
    @praveenkumarmaddeti6668 2 роки тому +3

    For Vx>1V --------> Ix = 0.
    For Vx

    • @vlsiorg
      @vlsiorg  2 роки тому +2

      Hi Praveen , thank you for pointing out. There is a correction needed in the last part of the graph.
      *For VX > 1V , Vx will be the drain , So VGS will be 1V and the mos will be on . Under this condition , for VX >=1V MOS will be in saturation.
      *For VX=1V IX=0 , VDS=0 here.
      *For VX < 1V , Vx wil be the source , under this condition , as rightly pointed out by you, we are at the edge of saturation. So for VX

    • @skyhawk3300
      @skyhawk3300 5 місяців тому

      @@vlsiorg For Vx>1, the MOS is in saturation, but (Vgs-Vt) = 0, so by the square law, Ix should also be 0

  • @pavankori6986
    @pavankori6986 2 роки тому

    Hey when you make regarding this for correction in last paragraph??

  • @GeekSlayer72
    @GeekSlayer72 Рік тому

    If Vx is really high, we agree that the VDS is high and the MOS would be at saturation. However, VGS-VTH = (2V-1V)-1V = 0V, hence, shouldn't Ix= 0A?

    • @vlsiorg
      @vlsiorg  Рік тому

      Hi.
      I am not use if i understand your question correctly.
      For VDS > 0 and Vgs-Vth =0(saturation) . There will be current .
      You can also look at it from the I-V curve perspective .
      Thanks

  • @vamsigirish4790
    @vamsigirish4790 2 роки тому

    Nice

  • @praveenkumarmaddeti6668
    @praveenkumarmaddeti6668 2 роки тому +1

    This plot is incorrect.
    Check once..

  • @VishalKumar-ii7jy
    @VishalKumar-ii7jy 2 роки тому

    Re-check please.

    • @vlsiorg
      @vlsiorg  2 роки тому

      Hi vishal , i have written the correction in the comments. I will soon make a update on this in my next video. Thank you 😃

    • @dhaneshprabhu72
      @dhaneshprabhu72 2 роки тому

      @@vlsiorg since the gate to source voltage is not more than threshold, will there be any current. That's my doubt