Simulating Verilog-A in Cadence | Tutorial

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  • Опубліковано 7 січ 2025

КОМЕНТАРІ •

  • @geekPlayground
    @geekPlayground 26 днів тому

    Thanks a lot for this amazing video. Liked and subscribed. 🙂
    Usually I don't watch videos that are this long but, in this case, I have watched every second !! In this area to explain well something, it cannot be done in 10 minutes! 🙂

  • @raphaelcardoso7927
    @raphaelcardoso7927 7 місяців тому +3

    It makes me really happy that you are still making useful content online that we can't easilly find. Keep on!

  • @mustafaghanim6552
    @mustafaghanim6552 6 місяців тому +1

    Thanks, your explanation is perfect.

  • @teavay-xl5hq
    @teavay-xl5hq 3 місяці тому

    Is it a nvim plugin you use for Verilog-A, or did you write a script by yourself?