Why PLL-based CDR?

Поділитися
Вставка
  • Опубліковано 4 січ 2025

КОМЕНТАРІ • 45

  • @rezamn4840
    @rezamn4840 2 роки тому +2

    I really like how you make it very simple and easy to understand and follow ! Much appreciated 🙏

  • @sumanchowdhury2724
    @sumanchowdhury2724 6 місяців тому +1

    Very good informative video. This gives a top-level picture . Can you also share your knowledge from Specs to design perspective. Looking at the Specs how to decide various critical parameters for different sub-blocks.

    • @circuitimage
      @circuitimage  6 місяців тому

      Hi SUMAN, thank you for the good suggestion. I'll do that since that would benefit lots of people as well. :)

  • @sunkarasaigoutham
    @sunkarasaigoutham 2 роки тому +1

    In reality, Din is generated from some sort of equalization since the received data swing is really small. Assuming this, to sample the edge and data we need two timed comparators. So those two can be inserted between Din and PD. PD takes edge and data info to produce early and late pulses that make VCO clock phase adjusted.

    • @circuitimage
      @circuitimage  2 роки тому

      Good comments. Yes or No :) That depends on your topology. Most of the published topology was applying what you said :)

  • @hermantheodorus7240
    @hermantheodorus7240 11 місяців тому +1

    Excellent video 😀

    • @circuitimage
      @circuitimage  11 місяців тому

      Hi Herman,
      Thank you so much for the kind words and I'm glad you liked it.
      Thanks,
      CC

  • @hrachya_khachatryan
    @hrachya_khachatryan Рік тому +1

    Nice video ! Two questions: 1) At 5:50 you mention that PFD has a wide pull-in range. What does this mean?
    2) At 7:48 you mention that frequency offset between VCO1 and VCO2 causes pulling phenomenon which can move VCO1 away from received data rate. How this happens? Thanks

    • @circuitimage
      @circuitimage  Рік тому +1

      Hi Hrachya, thank you for the good question. I have comments below. 😀
      1. The phase-frequency detector (PFD) would also detect the frequency offset than the (phase detector) only; therefore, a bigger frequency offset is much more tolerable in the PFD and that's what I meant that PFD has a wide pull-in range in a bigger frequency offset. 2. The received data rate would have a frequency offset from the VCO2 since the reference CKref has the frequency offset inherently from the far-end TX's reference CKref; therefore, the VCO2 would pull the VCO1's frequency while the VCO1 is trying to lock the input data.

    • @hrachya_khachatryan
      @hrachya_khachatryan Рік тому

      @@circuitimage thanks ))

    • @circuitimage
      @circuitimage  Рік тому

      @@hrachya_khachatryan You are very welcome.

  • @許育瑛-n5t
    @許育瑛-n5t 2 роки тому +1

    Thank for the sharing, I really appreciate it. I'd like to confirm one thing that the disadvantage of PLL is the litter peaking right. However, DLL-based CDR can eliminate the jitter peaking.

    • @circuitimage
      @circuitimage  2 роки тому +1

      Thanks for asking. Yes, your understanding is correct. The DLL-based CDR can eliminate the jitter peaking.

    • @許育瑛-n5t
      @許育瑛-n5t 3 місяці тому

      @@circuitimage Hi CC, how are you doing. There are some queries for PLL that I'd like to confirm with you.
      1.In general, PLL only in TX side, it won't be in the RX side, there is a CDR in RX side to recover the data and clock, may I know if it's correct.
      2.Since I've heard that there is DPRX_PHY, and I think there is only RX, but no TX, if it's correct, then may I know how to generate the high frequency and how to check the clock.
      Thanks a lot~

    • @circuitimage
      @circuitimage  3 місяці тому +1

      @@許育瑛-n5t Hi 育瑛,
      Thank you 🙏 for your good questions and I'm doing well. 😊
      I have comments below.
      1.In general, PLL only in TX side, it won't be in the RX side, there is a CDR in RX side to recover the data and clock, may I know if it's correct.
      [CC] No, the RX may have the PLL or share the same PLL with the TX depending on the topology, which I present lots of different CDR. topologies. 😊
      2.Since I've heard that there is DPRX_PHY, and I think there is only RX, but no TX, if it's correct, then may I know how to generate the high frequency and how to check the clock. Thanks a lot~
      [CC] No. This also depends on your system. The DP is a unidirectional link. But you still can receive the DP data and retransmit it. This application is used a lot in the automotive display panel. 😊

    • @許育瑛-n5t
      @許育瑛-n5t 3 місяці тому

      @@circuitimage Hi CC, thanks for your reply.
      Regarding the 2nd questions, so it means even the PHY has RX only, then still can use PLL and CDR to get the data, but if it's RX only, then where does the data come from.

    • @circuitimage
      @circuitimage  3 місяці тому +1

      @@許育瑛-n5t Hi 育瑛,
      Thank you for your additional questions. If it's RX only, then the data comes from the its partner TX through a cable.
      Best regards,

  • @somanshumishra1961
    @somanshumishra1961 11 місяців тому +1

    Hi,
    Thanks for the wonderful explanation. Just a small question. Why isn't it enough to just have a PFD based PLL with Din as its input? Won't that directly give the recovered clock? I suppose only issue could be Din not toggling like the clock.

    • @circuitimage
      @circuitimage  11 місяців тому

      Hi Somanshu,
      Thank you so much for the kind words and good questions.
      You're correct that the issue is that the input data Din may not toggle all the time like the clock.
      Thanks,
      CC

  • @breezerlxd
    @breezerlxd Рік тому +1

    Hi, Chen Really appreciate all the nice videos! They are very concise and informative and I really like the style you presenting them! I will pause to think about for 5 seconds when I am doing almost anything now. ;-) I have some questions. 1) first one is at 8:00 where you discuss two VCO PLL-based CDR. Since the far-end TX and local RX ref clocks will always have some frequency offset, ideally speaking the loop with VCO1 will be locking to the input data frequency and that means VCO1 will be running at slightly different frequency than VCO2, right? then I don't understand why this mismatch matters. 2) at 9:03 with single VCO but dual loop PLL-based CDR, I guess the VCO will lock to the local reference clock. Because of the frequency offset between far-end and local reference clocks, don't we still have the pulling effect you discussed earlier, meaning the phase acquisition loop will try to align the phase continuously to match the input data's phase but not locking to input data frequency. One last comment. Could you also provide a list of references at the end? it will be very helpful for people like me who know little about CDR but want to catch up and understand it more in details. Thanks a lot!

    • @circuitimage
      @circuitimage  Рік тому +1

      Hi Xiaodong,
      Nice to meet you. Thank you so much for your feedback and I'm glad my videos help. I have comments below.1) first one is at 8:00 where you discuss two VCO PLL-based CDR. Since the far-end TX and local RX ref clocks will always have some frequency offset, ideally speaking the loop with VCO1 will be locking to the input data frequency and that means VCO1 will be running at slightly different frequency than VCO2, right? then I don't understand why this mismatch matters. [CC] If both VCO's quality factors (Q) is not low, that's probably okay. But, if both VCO is LC VCO, the pulling effects would create lots of spur jitters or even frequency offset.2) at 9:03 with single VCO but dual loop PLL-based CDR, I guess the VCO will lock to the local reference clock. Because of the frequency offset between far-end and local reference clocks, don't we still have the pulling effect you discussed earlier, meaning the phase acquisition loop will try to align the phase continuously to match the input data's phase but not locking to input data frequency. [CC] Since there's only one VCO, there's no pulling effect between two VCOs. In this case, the pulling range of the phase acquisition loop (lock to input data w/ frequency offset) should cover the frequency offset, which must also lock to input data frequency in your design.3) One last comment. Could you also provide a list of references at the end? it will be very helpful for people like me who know little about CDR but want to catch up and understand it more in details. Thanks a lot![CC] Thank you so much for the very good suggestion, but most of my circuit images were based on what I've learned in our design project, so lots of materials cannot be shared. I don't quite remember which I've learned can be shared, if possible, in public. You can tell me a specific or general circuit, and I can find it for you specifically. 😀

    • @breezerlxd
      @breezerlxd Рік тому +1

      @@circuitimage Hi, CC Thanks for your reply! I understand now. No worries about the references. if i have questions, I leave them here. Thanks again for your help!

    • @circuitimage
      @circuitimage  Рік тому +1

      @@breezerlxd Thank you for your understanding. But, I'll still follow your great suggestion of putting some very basic references I've read in each topic, which may not be completely what I've learned but should be good enough for most audiences. :)😀

    • @breezerlxd
      @breezerlxd Рік тому

      @@circuitimage That will be great! Thanks a lot!

    • @circuitimage
      @circuitimage  Рік тому

      ​@@breezerlxd You're very welcome.😄

  • @jysun9290
    @jysun9290 11 місяців тому

    Hi Chen, nice video about pll-based CDR. On slide 11 about single-VCO dual-loop architecture, why do we have to switch from frequency loop to phase loop? Why can't we just let two loops operate at the same time? Also if we disconnect the frequency loop, as temperature and supply voltage variation slowly drift vco free-running frequency away, will false lock recur?

    • @circuitimage
      @circuitimage  11 місяців тому +1

      Hi JY,
      Thank you for the good feedback.
      Yes, you could keep both loops going at the same time, but there's an interaciton between two loops. So, there is a risk of instablitiy or pulling from the interaciton between two loops.
      Thanks,
      CC

    • @jysun9290
      @jysun9290 11 місяців тому

      @@circuitimage Hi Chen, thank you very much for the prompt response. You might have overlooked the last question in my comment: "Also if we disconnect the frequency loop, as temperature and supply voltage variation may slowly drift vco free-running frequency away, will false lock recur?" Is it an issue to be concerned?

    • @circuitimage
      @circuitimage  11 місяців тому

      Hi JY,
      You're very welcome. Thank you for the very good feedback.
      Yes, what you mentioned for the VCO frequency drift was real; therefore, the CDR loop must have the integral path to cover the slow temperature and supply voltage variation. TBH, I saw some paper's CDR removing the integral path and I don't think that would work in a long time. 😊
      Thanks,
      CC

    • @jysun9290
      @jysun9290 11 місяців тому

      @@circuitimage oh right, just as you mentioned in another video. Integral path can slowly pull VCO towards the slow frequency drift (luckily temperature and voltage variation is normally very slow). But since PD has limited capture range, we still need frequency acquisition loop to assist at first when frequency difference is big. Thank you so much Chen!

    • @circuitimage
      @circuitimage  11 місяців тому

      Correct 👍 You’re welcome ☺️

  • @nickliao7924
    @nickliao7924 2 роки тому +1

    benefit greatly!!!

    • @circuitimage
      @circuitimage  2 роки тому

      Thanks for the feedback. Let me know if you need more in other images. :)

  • @rangababuganta7725
    @rangababuganta7725 2 роки тому +1

    Can I say PLL based CDR loop latency is much smaller than PI based digital CDR ??. in this aspect can we say PLL based one is always better .? Could you explain in detail comparison between PLL based vs PI based CDR performance.
    Thank you Chen

    • @circuitimage
      @circuitimage  2 роки тому

      Thanks for the suggestions. Will do :)
      This may not be the case, but that can be done easily. The loop latency depends on how your CDR logic was designed and how those impairments were mitigated.

  • @sunkarasaigoutham
    @sunkarasaigoutham 2 роки тому +1

    @4:43 nice image on false detection which is real problem and taclked by PLL

    • @circuitimage
      @circuitimage  2 роки тому

      Thanks for let me know and I'm glad you like the image :)

  • @y_x2
    @y_x2 7 місяців тому +1

    Unable to understand anything...

    • @circuitimage
      @circuitimage  7 місяців тому

      Hi André, nice to meet you and thank you so much for your feedback. Could you please let me know your background or anything I can improve? I hope I can make a much clear to everyone in another video with your help. :)