Hi Mr. chen, Thanks for sharing your knowledge, if you can, please guide me how to estimate PI-base CDR RJ on jitter budget? =>i think PI-baseCDR_Rj roughly estimate can be =(PLL_Rj^2+PI_Rj^2)^0.5 ,right?
Thank you for your sharing about PI knowledge, I really appreciated it, and there are some questions I want to inquire to you. 1.During the introduction of PI, you mentioned there are 8 phases, is it fixed or could it be more phases than 8 2. In the video, you mentioned that every CDR loop may require a PLL to achieve the feature, so does it mean if there are three channels, then it needs three PLLs 3. In the video, you also mentioned that Wi will select two input reference clocks, like CKin0 and CKin1. Afterwards, the selected clock(CKin0, CKin1) by Wi will go through the VCO and send it to PD again, so that we can get clock recovery. I'm not sure it's correct or not Thank you again for everything you've done
Thanks for the feedback. I have comments below. 1. Yes, you could have more than 8 phases as the PI's basis, but the complexity is too high in a multi-phase VCO. Both phase noise or frequency may not be feasible. 2. Yes. If a PLL-based CDR, you may have three RX PLLs in three channels. See: ua-cam.com/video/ZJkadLjOg2s/v-deo.html 3. No, the selected clock(CKin0, CKin1) by Wi will go through the PI's input to generate a finer phase of CKout. See slide #2 of ua-cam.com/video/FkoJwnAYbMs/v-deo.html
@@circuitimageHi Mr.Chen, I still have some questions. 1. Because PI can rotate at a rate equal to offset, PI can generate a fine phase of CKout right. But CKin0 and CKin1 are selected by Wi, seems like there is still a little variation range of phase for CKout, so if we increase more phases as input(like 15 or 20), it'll be more precise right, but it may let the circuit be complicated. 2. Once Din inputs into PI system, it'll be generated a CKref by MP-PLL to PI, and CKref will be screened out two CKin by Wi, and then we can get the CKout, is it correct. Thank you very much.
@@許育瑛-n5t Thanks for those good questions. 1. You are correct. So, the Wi should be in the CDR loop. The Wi is dynamic changing as well to cover the offset. 2. That's correct
Hello Mr Chen, In one of the IPs we designed with PLL based CDR, we were able to tolerate +/-300ppm (and actually can tolerate 8x than this) of frequency offset between the TX and RX clock. How much range would a typical PI based CDR has?
Thank you so much for such high quality videos
Glad you like them!
Hi Mr. chen,
Thanks for sharing your knowledge,
if you can, please guide me how to estimate PI-base CDR RJ on jitter budget?
=>i think PI-baseCDR_Rj roughly estimate can be =(PLL_Rj^2+PI_Rj^2)^0.5 ,right?
Hi DT, you ballpark estimation of the total RJ is correct to me since both RJ are indepedent.
Can u talk more about later ( 9.17/11.38 in video). about Latency !!
Thank you Chen
Yes, that was on the plan and thanks for the reminder.
Thank you for your sharing about PI knowledge, I really appreciated it, and there are some questions I want to inquire to you.
1.During the introduction of PI, you mentioned there are 8 phases, is it fixed or could it be more phases than 8
2. In the video, you mentioned that every CDR loop may require a PLL to achieve the feature, so does it mean if there are three channels, then it needs three PLLs
3. In the video, you also mentioned that Wi will select two input reference clocks, like CKin0 and CKin1. Afterwards, the selected clock(CKin0, CKin1) by Wi will go through the VCO and send it to PD again, so that we can get clock recovery. I'm not sure it's correct or not
Thank you again for everything you've done
Thanks for the feedback. I have comments below.
1. Yes, you could have more than 8 phases as the PI's basis, but the complexity is too high in a multi-phase VCO. Both phase noise or frequency may not be feasible.
2. Yes. If a PLL-based CDR, you may have three RX PLLs in three channels. See: ua-cam.com/video/ZJkadLjOg2s/v-deo.html
3. No, the selected clock(CKin0, CKin1) by Wi will go through the PI's input to generate a finer phase of CKout. See slide #2 of ua-cam.com/video/FkoJwnAYbMs/v-deo.html
@@circuitimage Thank you for replying, it's really helpful
@@許育瑛-n5t I'm glad it helps :)
@@circuitimageHi Mr.Chen, I still have some questions.
1. Because PI can rotate at a rate equal to offset, PI can generate a fine phase of CKout right. But CKin0 and CKin1 are selected by Wi, seems like there is still a little variation range of phase for CKout, so if we increase more phases as input(like 15 or 20), it'll be more precise right, but it may let the circuit be complicated.
2. Once Din inputs into PI system, it'll be generated a CKref by MP-PLL to PI, and CKref will be screened out two CKin by Wi, and then we can get the CKout, is it correct.
Thank you very much.
@@許育瑛-n5t Thanks for those good questions.
1. You are correct. So, the Wi should be in the CDR loop. The Wi is dynamic changing as well to cover the offset.
2. That's correct
Hello Mr Chen,
In one of the IPs we designed with PLL based CDR, we were able to tolerate +/-300ppm (and actually can tolerate 8x than this) of frequency offset between the TX and RX clock. How much range would a typical PI based CDR has?
Good question. That depends on the PI's performance.
Tqs Chen
Hi Narendra, nice to meet you and thank you so much for your feedback.