Hi Tim, Thanks for you kindly explanation. I have some questions about this video. 1.) What's CCB, I do not see any explanation in the video. 2.)Could you do the active clamp flyback topology? I am very curious about how to choose the C(clamp capacitor) value and how to set the voltage. 3.) The RCD Snubber on the secondary side is the same as primary side? or something different? 4.) What's the best design in the RCD snubber, do you have any suggestion? because I am not sure how to balance the voltage and power dissipate.
CCB is capacitor charge balance. I will get to an active clamp flyback eventually. Secondary side RCD snubber is pretty much the same as primary. The best design is dependent on the switch. When you're balancing Vsn and snubber loss, effectively it boils down to minimizing the sum of snubber, conduction, and switching loss for that switch. Switches with higher blocking voltages may have slower transition times. There is no "best" design that I can give you to you without context.
@@timmcrae3831 Thanks for your answer, I have tow more question, 1.) when Dsn turn on, the current through Dsn will divide two current path right? one is flow through Csn, one is flow through Rsn? 2.) Do you have video talking about QR flyback, I am very curious about how to design it.
Can you suggest me best snubber design VALUES for Lleak = 180nH , Primary inductance with 0.9uH and secondary with 57uH in 1:8 turns ratio with Voltage spike of 242V at Vds whereas my Mosfet is can handle upto 200V my Vin_max is 9V and my Vout expected is 120V at Secondary Side with switching frequency of 1.5MHz and 12A Primary Peak current , Primary Current Mean =3A.I have designed it by 2nF and 40ohm snubber,my peak has been reduced but the power dissipation is too high than expected ..I need power dissipation less than 500mW at snubber.Can you help me with optimal Values.
This is one way of thinking about it. Either you use a very high voltage switch, or you use a lower voltage switch in conjunction with a snubber. Passive snubbers introduce some loss, but there's a tradeoff between this additional loss and the loss associated with a larger switch.
While measuring leakage inductor of a transformer, I shorted the secondary and tertiary windings but the reading went from 10mH to 7mH. Is 7mH the leakage inductance of the transformer or am I measuring wrong. Transformer - Epcos EE13/6/6.15 core, Primary 10mH gapped core 256 turns, secondary 9 turns, tertiary 24 turns. When I did this for a larger transformer with ungapped core, I got about 5% leakage inductance but in gapped cores, I feel that I have to measure leakage inductance in some other way.
Cool question, I haven't really discussed transformer measurement yet. Just a warning that this explanation is coming off the top off my head. I don't know what your measurement set up is, so I can't diagnose all your issues, but maybe I can give you some theoretical backing. First of all, leakage inductance of 7 mH seems quite large. Perhaps you mean 7 uH? It usually helps to consider the "T" or "pi" models of a transformer to understand how to measure the magnetizing and leakage inductances. For multi-winding transformers it gets a little more complex to manipulate. We can do an open circuit test to determine the leakage inductance and magnetizing inductance (L_lk,1 + L_mag) seem from (let's say) the primary winding. Then you can do short circuit tests for each winding to determine the leakage of that winding along with the reflected leakages of the other windings in parallel with the magnetizing inductance seen from that winding (L_lk,k + (n_1/n_k)^2L_mag || (n_2/n_k)^2L_lk,1 || ... || (n_k-1/n_k)^2L_lk,k-1 ). Shorting the secondary and tertiary windings will make the apparent inductance seen from the primary decrease because you're effectively removing the magnetizing inductance from the measurement. Measure the other windings and see what happens. The amount of leakage will definitely depend on core geometry and winding/turn placement. I think the fact that gapless cores will have a much larger magnetizing inductance compared to gapped cores (typically) is what increases that percentage. The leakage inductance does not change much if a small gap is introduced, but the magnetizing inductance tends decrease significantly due to the total reluctance of the transformer being dominated by the gap reluctance. Good luck!
It doesn't go away, this was more of a convenience to demonstrate the current paths which effect the ringing phenomenon. When the voltage across the voltage across the transistor reaches Vg+Vout/n, the voltage across the primary side of the transformer reaches Vout/n. Assuming the diode on the secondary side is ideal, it begins conducting. When this happens, the current in the magnetizing inductance can now flow to the output and by small ripple approximation, the voltage across the primary side of the transformer remains relatively constant at Vout/n. Effectively this creates two loops of interest. One loop is the magnetizing inductance discharging into the output, and the other is the leakage inductance flowing into the switch. The magnetizing inductance current tends only to flow to the output and not into the switching, allowing us to ignore it in the leakage inductance loop.
Excellent explanations. I like this infinite black table style :) This deserves much more views count ;)
Thanks for this, your content is too good to be on UA-cam. I hope yo keep doing this type of stuff!
Thanks for amazing explanation, I have my exams tomorrow, this helped a lot.
Awesome Vid ty. It finally makes sense to me.
Thank you for this video!
excellent explanation sir
Thanks for the video, could you please explain how the snubber capacitor gets charged to Vsn initially, I mean through which path?
Hi Tim,
Thanks for you kindly explanation.
I have some questions about this video.
1.) What's CCB, I do not see any explanation in the video.
2.)Could you do the active clamp flyback topology? I am very curious about how to choose the C(clamp capacitor) value and how to set the voltage.
3.) The RCD Snubber on the secondary side is the same as primary side? or something different?
4.) What's the best design in the RCD snubber, do you have any suggestion? because I am not sure how to balance the voltage and power dissipate.
CCB is capacitor charge balance.
I will get to an active clamp flyback eventually.
Secondary side RCD snubber is pretty much the same as primary.
The best design is dependent on the switch. When you're balancing Vsn and snubber loss, effectively it boils down to minimizing the sum of snubber, conduction, and switching loss for that switch. Switches with higher blocking voltages may have slower transition times. There is no "best" design that I can give you to you without context.
@@timmcrae3831 Thanks for your answer, I have tow more question,
1.) when Dsn turn on, the current through Dsn will divide two current path right? one is flow through Csn, one is flow through Rsn?
2.) Do you have video talking about QR flyback, I am very curious about how to design it.
Pls can u explain the snubber RC across the inductance or the MOSFET which one is effective .
Can you suggest me best snubber design VALUES for Lleak = 180nH , Primary inductance with 0.9uH and secondary with 57uH in 1:8 turns ratio with Voltage spike of 242V at Vds whereas my Mosfet is can handle upto 200V my Vin_max is 9V and my Vout expected is 120V at Secondary Side with switching frequency of 1.5MHz and 12A Primary Peak current , Primary Current Mean =3A.I have designed it by 2nF and 40ohm snubber,my peak has been reduced but the power dissipation is too high than expected ..I need power dissipation less than 500mW at snubber.Can you help me with optimal Values.
So snubbers help keep switches from failing ?.
This is one way of thinking about it. Either you use a very high voltage switch, or you use a lower voltage switch in conjunction with a snubber. Passive snubbers introduce some loss, but there's a tradeoff between this additional loss and the loss associated with a larger switch.
Great tutorial! Quick question.
How does one estimate the minimum required reverse voltage (VRRM) spec for the snubber diode?
The snubber diode needs to block Vg + Vsn when the main switch is on. You probably also want to include some extra on that for safety.
Awesome. Thanks for your reply.
While measuring leakage inductor of a transformer, I shorted the secondary and tertiary windings but the reading went from 10mH to 7mH. Is 7mH the leakage inductance of the transformer or am I measuring wrong.
Transformer - Epcos EE13/6/6.15 core, Primary 10mH gapped core 256 turns, secondary 9 turns, tertiary 24 turns.
When I did this for a larger transformer with ungapped core, I got about 5% leakage inductance but in gapped cores, I feel that I have to measure leakage inductance in some other way.
Cool question, I haven't really discussed transformer measurement yet. Just a warning that this explanation is coming off the top off my head. I don't know what your measurement set up is, so I can't diagnose all your issues, but maybe I can give you some theoretical backing.
First of all, leakage inductance of 7 mH seems quite large. Perhaps you mean 7 uH?
It usually helps to consider the "T" or "pi" models of a transformer to understand how to measure the magnetizing and leakage inductances. For multi-winding transformers it gets a little more complex to manipulate. We can do an open circuit test to determine the leakage inductance and magnetizing inductance (L_lk,1 + L_mag) seem from (let's say) the primary winding. Then you can do short circuit tests for each winding to determine the leakage of that winding along with the reflected leakages of the other windings in parallel with the magnetizing inductance seen from that winding (L_lk,k + (n_1/n_k)^2L_mag || (n_2/n_k)^2L_lk,1 || ... || (n_k-1/n_k)^2L_lk,k-1 ).
Shorting the secondary and tertiary windings will make the apparent inductance seen from the primary decrease because you're effectively removing the magnetizing inductance from the measurement. Measure the other windings and see what happens.
The amount of leakage will definitely depend on core geometry and winding/turn placement. I think the fact that gapless cores will have a much larger magnetizing inductance compared to gapped cores (typically) is what increases that percentage. The leakage inductance does not change much if a small gap is introduced, but the magnetizing inductance tends decrease significantly due to the total reluctance of the transformer being dominated by the gap reluctance.
Good luck!
Hi Tim, thank you for educating us... Is there a way I may contact u may be by email or other mode....Thx in advance....
Why does the magnitizing inductance go away when Vq equals Vg + Vout/n.
It doesn't go away, this was more of a convenience to demonstrate the current paths which effect the ringing phenomenon.
When the voltage across the voltage across the transistor reaches Vg+Vout/n, the voltage across the primary side of the transformer reaches Vout/n. Assuming the diode on the secondary side is ideal, it begins conducting. When this happens, the current in the magnetizing inductance can now flow to the output and by small ripple approximation, the voltage across the primary side of the transformer remains relatively constant at Vout/n.
Effectively this creates two loops of interest. One loop is the magnetizing inductance discharging into the output, and the other is the leakage inductance flowing into the switch. The magnetizing inductance current tends only to flow to the output and not into the switching, allowing us to ignore it in the leakage inductance loop.
@@timmcrae3831Thanks. I understand it now.
nice
Doud this is forward
VOR formula is wrong, it is Vo times N
While explaining the waveforms you have to explain still more clearly, i am unable to understand