Great explanation. The circulating current on the secondary side of the DAB was explained, what about the circulation current on the primary side of the DAB? A graphical representation of this will be highly regarded
Hello Tim, many thanks for these videos. Please I need an explanation of the circuit analysis of dual active half bridge circuits just as you did for dual active full bridge converters. Is there any material that can be recommended. thanks a lot
Thank you for the explanation!!! However, I am not able to understand one thing: at t1(-) when the current is positive, can't it flow through the diode, even when Qc is conducting?
This is actually possible. The way you'd determine if the FET was conducting through its body diode or through the channel is if I*R_on > V_f. Typically you'd select switches with R_on low such that even at peak current the voltage voltage drop across the on resistance is less than the forward voltage drop. On top of that, the fact that the current is AC means that for a portion of time the current is near zero, meaning that voltage drop would be quite low even if the R_on was large.
Dear Tim McRae, I have one more question. It is possible to have ZVS, also on the primary side?: Assume that the current is positive through inductance and we are switching off Q4 and turning on Q3, while Q1 is always ON during the latter switches.
Yup, ZVS is definitely possible on the primary side. The negative current at the beginning of the switching cycle (and the inverse at Ts/2) allows you to delay the turn on of Q1/Q4 and let the body diodes conduct (or really the snubber/switch output capacitance to discharge) before turning on the complementary switches.
Thank you very much! it helps me a lot! I am trying to build a DAB converter, but the power loss is still very high. The temperature of MOSFET increases very fast. I think it's because of turn OFF losses. Do you have some advice on how to reduce the turn OFF losses. Thank you, Tim!
I would say a good first step is to do a rough loss analysis to give yourself an estimate for what the losses should be for your specific operating condition. Unfortunately, there are many components that contribute to overall loss so it isn't so easy for me to suggest how you might fix this. What I will say is that you check your gate drivers and ensure they are operating as expected. Choosing a gate driver with a higher source/sink current (or a FET with a lower Qg) can reduce the turn on/turn off time of your FETs which will reduce switching loss. It is also possible that you haven't included enough dead time and have some shoot-through current. Without doing calorimetric testing of each component, you could verify if switching loss is a main contributor to loss by inspecting light load operation of the converter. By operating in light load, you tend to reduce conduction losses. Switching losses, which a less load dependent, remain high and you can give yourself an estimate of how much they are. In any case, beginning with a rough analysis to give yourself an idea of what to expect will make it much easier to debug board issues as they arise.
Thanks you for the explication , i hope you could make an exemple for designing the leackage inductor and how to chose a phase shift for a desired power 😃
Hi, according to your statements in the last part of the video you say "with Phase shift modulation we cannot achieve ZCS". Did I get correctly? Please confirm. Thanks
maybe yes maybe not. The pdf didn't explain it, but it said it's load dependent. I think because of the high dv/dt when have phase shift control cause that.
Thank you Mr McRae! So, if I correctly understand, at time t1 that correspond to the phase shift we turn off two MOSFETs with P=1/2*V2*IL(t1)*toff*fs (so V2 is high and the power losses are high) while we turn on two MOSFETs with P=1/2*VF*IL(t1)*ton*fs (so VF is low and the power losses are low). Is it correct? Thank you again for this explaination.
Yeah, and you're able to get this lower voltage of Vf because turning off the MOSFET pair forces the inductor to commutate to the opposite set of diodes due to the direction of current.
Great explanation.
The circulating current on the secondary side of the DAB was explained, what about the circulation current on the primary side of the DAB? A graphical representation of this will be highly regarded
Great video! Is it possible to share reference for ZCS on DAB for input and output bridges, please?
Hello Tim, many thanks for these videos. Please I need an explanation of the circuit analysis of dual active half bridge circuits just as you did for dual active full bridge converters. Is there any material that can be recommended. thanks a lot
very informative video. i am currently doing the state space average model of DAB. Could you please tell me which material to follow ?
www.pes-publications.ee.ethz.ch/uploads/tx_ethpublications/Krismer_2011_03_17_Modeling_and_Optimization_of_Bidirectional_Dual_Active_Bridge_DC-DC_Converter_Topologies.pdf
Thanks TIM great Explanation! simple and precise...👏
Thank you for the explanation!!! However, I am not able to understand one thing: at t1(-) when the current is positive, can't it flow through the diode, even when Qc is conducting?
This is actually possible. The way you'd determine if the FET was conducting through its body diode or through the channel is if I*R_on > V_f. Typically you'd select switches with R_on low such that even at peak current the voltage voltage drop across the on resistance is less than the forward voltage drop.
On top of that, the fact that the current is AC means that for a portion of time the current is near zero, meaning that voltage drop would be quite low even if the R_on was large.
@@timmcrae3831 thank you very much.
Dear Tim McRae, I have one more question. It is possible to have ZVS, also on the primary side?:
Assume that the current is positive through inductance and we are switching off Q4 and turning on Q3, while Q1 is always ON during the latter switches.
Yup, ZVS is definitely possible on the primary side. The negative current at the beginning of the switching cycle (and the inverse at Ts/2) allows you to delay the turn on of Q1/Q4 and let the body diodes conduct (or really the snubber/switch output capacitance to discharge) before turning on the complementary switches.
Can u please send me simulation model
Thank you very much! it helps me a lot! I am trying to build a DAB converter, but the power loss is still very high. The temperature of MOSFET increases very fast. I think it's because of turn OFF losses. Do you have some advice on how to reduce the turn OFF losses. Thank you, Tim!
I would say a good first step is to do a rough loss analysis to give yourself an estimate for what the losses should be for your specific operating condition.
Unfortunately, there are many components that contribute to overall loss so it isn't so easy for me to suggest how you might fix this.
What I will say is that you check your gate drivers and ensure they are operating as expected. Choosing a gate driver with a higher source/sink current (or a FET with a lower Qg) can reduce the turn on/turn off time of your FETs which will reduce switching loss. It is also possible that you haven't included enough dead time and have some shoot-through current.
Without doing calorimetric testing of each component, you could verify if switching loss is a main contributor to loss by inspecting light load operation of the converter. By operating in light load, you tend to reduce conduction losses. Switching losses, which a less load dependent, remain high and you can give yourself an estimate of how much they are.
In any case, beginning with a rough analysis to give yourself an idea of what to expect will make it much easier to debug board issues as they arise.
Thanks you for the explication , i hope you could make an exemple for designing the leackage inductor and how to chose a phase shift for a desired power 😃
Hi, according to your statements in the last part of the video you say "with Phase shift modulation we cannot achieve ZCS". Did I get correctly? Please confirm. Thanks
maybe yes maybe not. The pdf didn't explain it, but it said it's load dependent. I think because of the high dv/dt when have phase shift control cause that.
and i still confused with this lmao
Thank you for the reupload.
When Will u update the new video
Unfortunately, future updates are a little unclear.
@@timmcrae3831 so sad to hear about it. Your video is really helpful. Hope u can continue to make this kind of video such as CLLC
you are doing great. may you please guide how to find leakage inductance
Thank you Mr McRae! So, if I correctly understand, at time t1 that correspond to the phase shift we turn off two MOSFETs with P=1/2*V2*IL(t1)*toff*fs (so V2 is high and the power losses are high) while we turn on two MOSFETs with P=1/2*VF*IL(t1)*ton*fs (so VF is low and the power losses are low). Is it correct? Thank you again for this explaination.
Yeah, and you're able to get this lower voltage of Vf because turning off the MOSFET pair forces the inductor to commutate to the opposite set of diodes due to the direction of current.
Hey! Really liked the details!! Thank you for sharing :)
too good
U can prepare drawing first, so not to waist time
u can fast forward and watch