Thank you for being a part of my channel. Long back when I didn't have acces to tools I had used Edaplayground. Later I never used. With this tool you can simulate your code. Now I have no idea whether the tools have been updated or the same one. Its better to use free version of XILINX ise or modelsim than Edaplayground. So if you have these free simulator or any other simulator then it's better not to use Edaplayground. Thanks.
If you visit XILINX or mentor graphics(modelsim) you can freely download students version of their simulator. Try once. Else search it on Google www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive-ise.html
At 8:32, u wrote all the statement inside always block execute sequentially, i didnt get that point, if there are multiple statement it will depend on the type of statement, if blocking all statement will execute sequentially, but if non blocking then it will not execute parallely na. i have a doubt at this point, can u clearify.
In reality, always@ doesn't represent any hardware. So it's executed at simulator level and in simulator everything are executed sequentially and not parallely.(The statement you mentioned , consider it this way). But at hardware level it's different.sequential is a misguided term we have been using in verilog and tells nothing about hardware execution. always @(clk) X= y+z; P= X+a; always @(clk) X
@@ComponentByteif both statement have #1 sec delay, then in blocking 1st statement will get executed at 1 sec and second at 2 sec, while in non blocking both will get executed at 1sec. Is my statement true? Or is it like in blocking also both start at 0 just that for completion second statement require 2 sec while first get completed at 1 sec.
You are correct and these are all simulator level execution which depends on time. If you are talking about #1 or #2 kind of statement then at hardware level these are ignored like they don't exist and then statement are executed based on data dependency. So you are correct at simulator level(but at hardware level you may not be correct). I am trying to explain you at transistor level or RTL level. It seems you are very much interested in learning verilog. Keep on exploring.
Hey, I will upload all the Verilog concepts . Thanks for the concern but I will also upload the Electronics hardware concepts like sensor, Electronics components like R,C,BJT, OPAM,BATTERY etc and electronic circuit design concepts...
sir you are saying that statements inside procedural block execute when the sensitivity of the events in the always block changes. so i want to know how will we or how the sensitivity of those events change?
Whatever present in sensitivity list are usually inputs. In real-time world , let's say your mobile phone's touch screen, when you touch screen, something happens. So your input is inside the sensitivity list ( say Sensor's input) so when input changes means when screen is touched, it enters body of always block and some logic is implemented like screen glowing. The inputs may come from either outside or due to the effect of some internal effect. Hope it helps.
Thank you for appreciation. The truth is my native is not Hindi, so I speak Hindi but with grammatical mistakes. I am not very good at English but I somehow manage to speak English with some error and you can easily spot my different accent due to my native language. So I decided to make verilog videos in English thinking in mind at least all verilog earners understand English language and it will reach maximum people as verilog tutorial was hard to find on UA-cam. But next , I will make all my videos in Hindi language. Thanks.
clk can be any signal and when any changes in this clk signal i.e. 1 to 0 or 0 to 1 or only 1 or only 0 happen then always block is executed. Posedge clk means when positive edges(only edges) of a signal named clk comes then always block is executed.
Explained in simple language. Thanks
Yes, friend he had nicely explained the concepts....
Till this video I had go throughout this series. Thanks for content...
Hope you will upload video based on how to use edaplayground for verilog
Thank you for being a part of my channel.
Long back when I didn't have acces to tools I had used Edaplayground. Later I never used. With this tool you can simulate your code. Now I have no idea whether the tools have been updated or the same one.
Its better to use free version of XILINX ise or modelsim than Edaplayground.
So if you have these free simulator or any other simulator then it's better not to use Edaplayground. Thanks.
@@ComponentByte Can you make video on *how to download and install free version of Xilinx ise and Modelsim* ?
If you visit XILINX or mentor graphics(modelsim) you can freely download students version of their simulator. Try once.
Else search it on Google
www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive-ise.html
At 8:32, u wrote all the statement inside always block execute sequentially, i didnt get that point, if there are multiple statement it will depend on the type of statement, if blocking all statement will execute sequentially, but if non blocking then it will not execute parallely na. i have a doubt at this point, can u clearify.
In reality, always@ doesn't represent any hardware. So it's executed at simulator level and in simulator everything are executed sequentially and not parallely.(The statement you mentioned , consider it this way).
But at hardware level it's different.sequential is a misguided term we have been using in verilog and tells nothing about hardware execution.
always @(clk)
X= y+z;
P= X+a;
always @(clk)
X
@@ComponentByteif both statement have #1 sec delay, then in blocking 1st statement will get executed at 1 sec and second at 2 sec, while in non blocking both will get executed at 1sec. Is my statement true? Or is it like in blocking also both start at 0 just that for completion second statement require 2 sec while first get completed at 1 sec.
You are correct and these are all simulator level execution which depends on time. If you are talking about #1 or #2 kind of statement then at hardware level these are ignored like they don't exist and then statement are executed based on data dependency.
So you are correct at simulator level(but at hardware level you may not be correct).
I am trying to explain you at transistor level or RTL level.
It seems you are very much interested in learning verilog. Keep on exploring.
@@ComponentByte ok, I got it. Thanks for your time and answering my query everytime
Hi, you changed your channel name. are u not going to upload verilog tutorial anymore ?
Hey, I will upload all the Verilog concepts . Thanks for the concern but I will also upload the Electronics hardware concepts like sensor, Electronics components like R,C,BJT, OPAM,BATTERY etc and electronic circuit design concepts...
Learned a lot.Thanx. can u please explain more how it is used for combinational and sequential logic
Very soon I m going to upload separate videos for combinational and sequential logic implementation using always block
Yes, friend he had nicely explained the concepts....
Your explanation is good,could you upload more videos
This month onwards I will upload the full content.Thanks
Yes, friend he had nicely explained the concepts....
sir you are saying that statements inside procedural block execute when the sensitivity of the events in the always block changes. so i want to know how will we or how the sensitivity of those events change?
Whatever present in sensitivity list are usually inputs. In real-time world , let's say your mobile phone's touch screen, when you touch screen, something happens. So your input is inside the sensitivity list ( say Sensor's input) so when input changes means when screen is touched, it enters body of always block and some logic is implemented like screen glowing. The inputs may come from either outside or due to the effect of some internal effect.
Hope it helps.
@@ComponentByte yes got it thanks. so basically the events inside the always block would be the inputs always, right?
If input changes then only we get output.
Thanks a lot for this tutorial
Thank you for explaining about varilog . you should make these tutorial in hindi language also.again thank you very much
Thank you for appreciation.
The truth is my native is not Hindi, so I speak Hindi but with grammatical mistakes. I am not very good at English but I somehow manage to speak English with some error and you can easily spot my different accent due to my native language.
So I decided to make verilog videos in English thinking in mind at least all verilog earners understand English language and it will reach maximum people as verilog tutorial was hard to find on UA-cam.
But next , I will make all my videos in Hindi language.
Thanks.
$display is used in always block ,it doesn't diisplay anything,not getting output,why sir
$display is used in testbench and not in main module. It's not used inside always block.its used inside intial block.
Nicely explained. Thanx
Yes, friend he had nicely explained the concepts....
What is the difference between always@(clk) and always@(posedge clk)
clk can be any signal and when any changes in this clk signal i.e. 1 to 0 or 0 to 1 or only 1 or only 0 happen then always block is executed.
Posedge clk means when positive edges(only edges) of a signal named clk comes then always block is executed.
Great video sir.
Thank you.
can we have pdf of this ppt?
ppt can't be shared, really sorry.
Good one, thanx
Yes, friend he had nicely explained the concepts....
Pls provide the pdf of whole lecture, if it’s possible