Everytime I admire your verilog explanation skill. These are difficult concepts but you have great skill to make me understand. I learn not only verilog concepts but also realtime hardware meaning of all verilog concepts. These concepts are rare to find. Be my teacher. Thank you so much
Thank you for your words. I am trying my best to share the knowledge I have gained over the years. So you try your best learn what you want to learn. Keep learning and keep sharing.
I am very thankful to you. Because it is very difficult to search all these concepts and their differences, but you made it easy . Very happy to be your subscriber...
@22:40 sir u told that 33ns will be reflected at 38ns but according to intra-assignment delay it will not detect and reflect any changes till 35ns (30+5) then after that output will remain 1 till 36ns. At that time since input is changed, it will again reflect it at 41ns till then output will be its old value which is 1. After 41ns since input =1 thus output continues to remain 1 till 50ns. Pls correct, if my explanation is wrong!!
Best explanation so far on this topic. Every time I learn new concepts from you. From where did you learn these concepts(any material or references). Thanks a lot.
Thanks for your valuable comments. I don't remember from where I learned but it's worth knowing so shared with you all.keep watching and you will learn lot. Thanks
you said for interassignment delay that if within 3 sec input a or b changes then module will not give correct output. but this is wrong it is valid for intraassignment delay.... source Verilog by samir palnitkar it is mentioned in that that with the delay specified for the interassignmt if the input changes in between then output will be affected
Inter-assignment delays are typically used to model timing control, such as assignments triggered on the edge of a clock, while intra-assignment delays, or wire delays, are used to simulate the propagation delay of signals through hardware. In practical hardware description, intra-assignment delays are more commonly used to model the delay of signals through logic gates or wires. Is that right?
Thanks. All the verilog concepts I will be covering in my upcoming tutorial, so keep watching for complete verilog concepts. I will also cover filter design, FPGA interfacing , few protocols.
Hi Thanks for your explanation I had a question: Does computational logic always follow C1 type waveform (inertial delay), as I was thinking that we should always have behavior same as C4 waveform for computational and sequential elements.
Delays are not synthesized and thus ignored by synthesis tools if any type of delay is mentioned while writing verilog code. So at code level, no delay exist. But at hardware level it exist. One is gate delay due to its manufacturing process which we can't ignore and other is wire delay due to the physical path or traces . This is the only delay we can take care of and is a valid delay . C
Dealys are never used while RTL coding. RTL code generates a hardware. Delays are used for simulation only i.e. while writing test bench. These are used for testing the logic written to validate the RTL code with different condition and configuration. Hope you got the point.
C2 and C4 waveforms are not same and I have provided the notes and explanation. In case of C2 the 1ns delay is ignored as it falls within assigned delay of 3ns as per the rules. In case of C4 the 1ns delay is considered and not ignored again as per hdl rule . So both have got different waveforms.
Everytime I admire your verilog explanation skill. These are difficult concepts but you have great skill to make me understand. I learn not only verilog concepts but also realtime hardware meaning of all verilog concepts. These concepts are rare to find. Be my teacher. Thank you so much
Thank you for your words. I am trying my best to share the knowledge I have gained over the years. So you try your best learn what you want to learn. Keep learning and keep sharing.
Yes friend, really nice videos....
I am very thankful to you. Because it is very difficult to search all these concepts and their differences, but you made it easy . Very happy to be your subscriber...
A big thank you for this excellent video and God bless you and your hardwork for sharing these verilog concepts.
it was really tough topic but now it is clear thanks bhai... thanks a lot
@22:40 sir u told that 33ns will be reflected at 38ns but according to intra-assignment delay it will not detect and reflect any changes till 35ns (30+5) then after that output will remain 1 till 36ns. At that time since input is changed, it will again reflect it at 41ns till then output will be its old value which is 1. After 41ns since input =1 thus output continues to remain 1 till 50ns. Pls correct, if my explanation is wrong!!
Hello, you are absolutely correct.
Thanks.
Best explanation so far on this topic. Every time I learn new concepts from you. From where did you learn these concepts(any material or references). Thanks a lot.
Thanks for your valuable comments. I don't remember from where I learned but it's worth knowing so shared with you all.keep watching and you will learn lot. Thanks
Dear friend, Veriog Primer by Jayaram Bhasker is a very good book. You can learn VHDL from VHDL primer authored by the same author....
understood clearly. thank you
Thanks so much!. It is very clear and helpful explaination.
Welcome. Happy learning.
Yes dear friend, really nice videos....
you said for interassignment delay that if within 3 sec input a or b changes then module will not give correct output. but this is wrong it is valid for intraassignment delay.... source Verilog by samir palnitkar it is mentioned in that that with the delay specified for the interassignmt if the input changes in between then output will be affected
Inter-assignment delays are typically used to model timing control, such as assignments triggered on the edge of a clock, while intra-assignment delays, or wire delays, are used to simulate the propagation delay of signals through hardware. In practical hardware description, intra-assignment delays are more commonly used to model the delay of signals through logic gates or wires.
Is that right?
Yes, you are right
Bruh really awsm video....
pls upload more video
it's awesome
Thanks. All the verilog concepts I will be covering in my upcoming tutorial, so keep watching for complete verilog concepts. I will also cover filter design, FPGA interfacing , few protocols.
Dear akash, you can find similar videos in my channel.....
Hi
Thanks for your explanation
I had a question: Does computational logic always follow C1 type waveform (inertial delay), as I was thinking that we should always have behavior same as C4 waveform for computational and sequential elements.
Delays are not synthesized and thus ignored by synthesis tools if any type of delay is mentioned while writing verilog code. So at code level, no delay exist. But at hardware level it exist. One is gate delay due to its manufacturing process which we can't ignore and other is wire delay due to the physical path or traces . This is the only delay we can take care of and is a valid delay .
C
@@ComponentByte Thanks, but if wire delay sonly delay, why do we use other types of delays ?
Dealys are never used while RTL coding. RTL code generates a hardware. Delays are used for simulation only i.e. while writing test bench. These are used for testing the logic written to validate the RTL code with different condition and configuration. Hope you got the point.
why this c2 & c4 have not same waveform? although c2 waveform has changed at 7th clock cycle but not at 8th clock cycle?
C2 and C4 waveforms are not same and I have provided the notes and explanation.
In case of C2 the 1ns delay is ignored as it falls within assigned delay of 3ns as per the rules.
In case of C4 the 1ns delay is considered and not ignored again as per hdl rule .
So both have got different waveforms.
pls upload more design problem in verilog code
nice
Thank you.
All cleared
👏👏👏