thanks for this video, can you also talk about sources of high frequency [and low frequency noise coming from VRM] in PDN design? we normally look at impedance at 20k to 20M for PCB, can you further develop noise sources for PDN over frequency range and higher than 20MHz? with current Nyquist rate being at 28GHz and 56GHz noise frequency seems to be very high frequency range than 20MHz.
Hi Shady, nice to meet you. Thank you so much for your good question and suggestions. The high frequency supply noise should be reduced well by the on die decap; therefore, that’s usually not an issue. Instead, the low frequency < 20MHz, supply noise must be reduced through off chip decap, which provides big cap area efficiently. Hopefully, this answers most of your questions easily without circuit images.
Your video quality is so high! Thank you
Thank you for the feedback and I'm glad you like it.
thanks for this video, can you also talk about sources of high frequency [and low frequency noise coming from VRM] in PDN design? we normally look at impedance at 20k to 20M for PCB, can you further develop noise sources for PDN over frequency range and higher than 20MHz? with current Nyquist rate being at 28GHz and 56GHz noise frequency seems to be very high frequency range than 20MHz.
Hi Shady, nice to meet you. Thank you so much for your good question and suggestions. The high frequency supply noise should be reduced well by the on die decap; therefore, that’s usually not an issue. Instead, the low frequency < 20MHz, supply noise must be reduced through off chip decap, which provides big cap area efficiently. Hopefully, this answers most of your questions easily without circuit images.