Nice video as always CC and pointing out advantages of FR DFE. With data rates going up and difficulty for PLL to generate FR clocks for Rx, HR clocking is becoming popular. E.g. for PCI-Gen5 32Gsps, I still see most PLL outputting 16GHz clock, so DFE then has to be HR.
Hi Abhirup, Thank you 🙏 so much for your feedback, which I agree with a lot. My PCI-Gen5 32Gbps also applied PLL's 16GHz clock.😊 I'll put your comments in my next video: "Why half-rate or quarter-rate DFE." 😊
The interface data rate can reach up to 100Gb/s per lane. If we use a full-rate decision feedback equalizer (DFE), generating a clock signal becomes challenging and requires significant power. Thus, achieving 200Gb/s could be difficult due to the complexity of generating a full-rate clock at such high speeds.
Hi 장구, Nice to meet you. Thank you 🙏 so much for your feedback, which I agree with a lot. I'll put your comments in my next video: "Why half-rate or quarter-rate DFE." 😊
Great content as always. I did note that slide 4 title has a typo. The slide title has "...Issue at the of the..." I assume you were debating to use "at" or "of". I'd suggest "of" as the phenomenon is not the location of the summers, but rather a property of having two summer instances.
Nice video as always CC and pointing out advantages of FR DFE. With data rates going up and difficulty for PLL to generate FR clocks for Rx, HR clocking is becoming popular. E.g. for PCI-Gen5 32Gsps, I still see most PLL outputting 16GHz clock, so DFE then has to be HR.
Hi Abhirup,
Thank you 🙏 so much for your feedback, which I agree with a lot. My PCI-Gen5 32Gbps also applied PLL's 16GHz clock.😊 I'll put your comments in my next video: "Why half-rate or quarter-rate DFE." 😊
@@circuitimage great, look forward CC.
@@abhiruplahiri1 Thanks for your always support. :)
The interface data rate can reach up to 100Gb/s per lane. If we use a full-rate decision feedback equalizer (DFE), generating a clock signal becomes challenging and requires significant power.
Thus, achieving 200Gb/s could be difficult due to the complexity of generating a full-rate clock at such high speeds.
Hi 장구,
Nice to meet you. Thank you 🙏 so much for your feedback, which I agree with a lot. I'll put your comments in my next video: "Why half-rate or quarter-rate DFE." 😊
Great content as always. I did note that slide 4 title has a typo. The slide title has "...Issue at the of the..." I assume you were debating to use "at" or "of". I'd suggest "of" as the phenomenon is not the location of the summers, but rather a property of having two summer instances.
Hi Matthew,
Nice to meet you. Thank you 🙏 so much for your corrections and for looking carefully, accidentally adding extra "the of".