#22 How to write TESTBENCH in verilog || use of $monitor, $display,$Stop,$finish in verilog

[@bibekmainali9834]

Very good and understandable explanation. Thank you sir.

[@BeMuslimOnly]

Excellent job❤

[@satyajeet_sakariya]

Very nice and neat explanation

[@ffushiguro]

sir we can put $time instead of simtime right whats the difference in that

[@ComponentByte]

Both gives simulation time but
time gives scaled times
Simtime gives unscaled times

[@speedypatel2905]

Hello sir,
I just want to ask you that what is %g %b and all?

[@ComponentByte]

These are called format specifier in verilog. %b for binary number and %g for general floating point or real number. These are used to represent a number in different format. Hope it helps. Happy learning.

[@speedypatel2905]

@@ComponentByte Ya okay, thanks, sir!

[@circuitsanalytica4348]

% generally define the data type associated with the identifiers, right?

[@abhishekbhadauriya8424]

@@ComponentByte sir, you need to explain more clearly this $monitor() part...you covered this part too fast.

[@ComponentByte]

Hello, thank you for your concern. This might have happened due to not to make long length video. But I can always clear your query if you have any on this topic.

[@radhikabandari4674]

Hello Sir,
I have a question. should the Testing vector be written after DUT instantiation..? In the 2nd approach $display approach, DUT is instantiated after Test Vector written inside initial block.
could you please clarify the execution steps in this case.

[@ComponentByte]

All the statements(except always block, blocking assignment) are executed parallely. So it doesn't matter whether after DUT or before DUT.
Thanks

[@teketinikhilkumar7905]

at the last example cant we write a.b in the place of reg i0,i1(inputs)

[@ComponentByte]

Yes, you can write a,b

[@teketinikhilkumar7905]

@@ComponentByte thank you sir

[@ffushiguro]

If u don't mind can u explain about questasim software too

[@ffushiguro]

I had a doubt like I done test bench and design file and called out the source too (unix commands) but if I want to compile it's saying like " can't read the design file there's no directory"pls help me bro

[@fatimamadar5575]

sir....i have doubt .....input is represented as Reg, and output is represented as wire....?

[@ComponentByte]

Yes, input is reg and output is wire because testbench module works as wrapper on top of your logic module and this input becomes output (reg) and output becomes input (wire).please check the diagram I have used to explain it.

[@andyden8501]

Simple explanation. Thanks.

[@circuitsanalytica4348]

Yes friend, very good tutorial....

[@雷克斯Rex]

13:17 module instantiation

[@sailaxmianumula4452]

Such a great explanation sir...Thank you so much.This video helped me alot

[@ComponentByte]

Welcome !
Wish you a happy learning.

[@ajaymajhi8429]

Thanks for sharing

[@circuitsanalytica4348]

Yes friend, really nice video tutorial....

[@priyashalini6422]

Sir please teach system verilog also and kindly digital electronics and uvm and Linux my humble request sir

[@ComponentByte]

I know Linux, perl scripting and even if I upload video on these topics i will hardly get views. So i should not upload video on these topics.
System verilog tutorial will consume more time which i can't afford right now.
For Digital electronics, i am planning but again the same story how many will be interested ?
Let's hope for better.

[@alekhyakonuri252]

very nice explanation sir

[@ComponentByte]

Thank you.

[@vishalmoladiya2735]

Thanks for this...

[@ComponentByte]

Welcome.

[@nithintm1641]

Thank u so much ❣️

[@circuitsanalytica4348]

Yes friend, nice tutorial....

[@pushparaj3240]

Good explanation

[@ComponentByte]

Thank you.

[@marshalraju6089]

Thanks a lot

[@chandrikaag8443]

Thank you ❤️

[@chandrikaag8443]

Best explanation

[@ComponentByte]

Welcome. Happy learning.

[@circuitsanalytica4348]

@@chandrikaag8443 yes best explanation, you are right....

[@saketkumar9852]

Love u bro

[@ComponentByte]

Thank you dear. Keep learning.

[@ejaz733]

Learn English properly

[@ComponentByte]

Still trying.
Sorry for the inconvenience.

[@bibekmainali9834]

He explained it well. You didn't understand?