COMPLETE TIMING CONSTRAINTS | PHYSICAL DESIGN |ASIC | ELECTRONICS | VLSIFaB

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A series of constraints applied to a given set of paths or nets that dictate the desired performance of a design. Constraints may be period, frequency, net skew, maximum delay between end points, or maximum net delay.
We have discussed different timing constraints with examples.
in the next video we will be discussing unconstrained endpoints and its importance.
Kindly Like share and subscribe the channel. (Just for motivation )
These constraints specify clock related definitions which affect synthesis and timing analysis.
VLSIfab playlist are given below:
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[@chintu8700]

good video about timing constraints, Tq VLSIFaB

[@VLSIFaB]

Welcome.. please share

[@abishekguggari1180]

Thank u sir

[@VLSIFaB]

Welcome

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[@User--jm5911]

Sir if you don't mind can you tell why hold check is in same clock cycle while setup check in next clock cycle

[@gaur31]

Nice 👍

[@VLSIFaB]

Thanks ✌

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[@pavankumarmvs6728]

very gud explanation. when we are mentioning clk uncertainity, why we are substracting from setup and for hold why we are adding that uncertainity. can you please give a bit information about ir

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[@rajashreejc1173]

Hi sir...good explanation..can you please provide details of more arguments of set_clock latency

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[@saivarma858]

Please make video on read verilog your videos are hepling for people like us who are freshers in VLSI industry

[@VLSIFaB]

Thanks.. surely will try to make videos .

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[@prasanthpasumarty8513]

Your explanation is really good.. can you send me the link where you have explained regarding unconstrained endpoints

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[@merrygo7189]

Hi ,,Can you tell me.. what is the use of unclocked flops ...?

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[@anushak5318]

can you send me the link where you have explained regarding unconstrained endpoints

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[@muralijha8703]

SIR you are TOO GOOOOOOOOOOOOD .PLZ KEEP ON MAKE VIDEOS

[@VLSIFaB]

Oh thanks..for your gooooood😛

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[@sanjusingertelugu9862]

hi sir will u provide classes on icc2 tool tq sir.

[@VLSIFaB]

Yah.. please paste the same comment in community section too.

[@shaileshkumar-gy4ue]

can u explain early and late switch plz

[@VLSIFaB]

Will explain it..

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[@srikanth6078]

Sir please give more details about these library files

[@VLSIFaB]

Sure.. Will make one video on library files

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[@pullepujaswanth5035]

can you create a video on library plz

[@VLSIFaB]

Yah sure..we are planning to start 5 minutes video series, in which we will include library also. Thanks for the suggestion.

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