Dear Sam, Thank you so much for all your videos and detailed explanations. It helped me so much to deeply understand a lots of processes in electronics!!! I become a really big fan of your lectures! Will it be possible to make a video about mosfet/igbt protections such us miller clamp and desaturation protection? Thank you.
Thank you for your time and for producing the videos. Could you please prepare a video on how to design and simulate a buck converter from scratch? Thank you.
Hello Professor! Thanks for the wonderful explanation. Im however getting stuck at one point. When you draw the small signal model using the purturbation at the gate why does the current in Coss flow from direction Source towards Drain and not the other way round. thankyou so much!
The main driving force of the Coss current is the dependent source of the MOSFET which, for a positive input, pulls the current to ground. The contribution of the gate current to Coss is negligible.
Nice presentation. I just don't get the point you mentioned at the last slide. You mentioned that the input impedance is resistive because the changes in the voltage dependent current source passes through Cgd regardless of the value of this capacitance. However, the flat region of Vgs happens only after Id already reached the load value and then the voltage is allowed to drop. To me, the change in Vds is what triggers the start of the flat region.
Professor Yaakov, i have some trouble to understand this topic on turn on. Could you please help me out. 1) In your Explanation you assume a delta Id during the VGS flat region. How is it possible to make this assumption. If i look at the characteristics of the turn on the current through the MOSFET is already Equal to the inductor current and constant during the VGS flat region. It doesnt change anymore. 2) After the miller plateau, the VGS rises until the maximum value. Why does the drain current stay constant? I understand that the drain current already reached the Max inductor current, but how do i explain it with typicall MOS equations? The drain current should rise as long as VGS rises. 3) Also again referring to Drain current equations. During the plateau VDS falls to 0. When VDS
To me, the previous video on gate charge was bit more intuitive. 1. Can you please explain why Cgs is no longer in the equivalent circuit? 2. Also, during the time Vds is dropping to zero, isn't Cgd being charged? It will be charged again after Vds reaches zero as well, what actually changed before and after-Only Cgs being charged additionally in the later half? 3. Is the Vgs constant due to the lower time constant (low Zin and Cgd)? The quality of video is fabulous as usual.
Hi Maksudul, Well this video was motivation by a comment stating that the guy still did not understand why the Vgs is flat. 1. Cgs was removed to get Zin and then was put back But I have wrongly labeled it as Cgd (thanks for noticing this). I will note this in the title page of video. 3. Yes but: Zin and Cgs (in practice it doe not make any difference since in both cases the time constant is in the nsec range)
@@sambenyaakov Thanks a lot Dr. Yaakov. Would you consider making a tutorial on (1) gate driver considerations with GaN MOSFETs and (2) Conducted EMI issues while designing PCBs? There are few tutorials on how to work around, but I was looking for something more intuitive. Thanks again.
Hi Thanks for explanation. I have few questions. 1. In general, what all is the miller capacitance affecting. Input cap of Mosfet will increase which will affect the previous driver , o/p cap will also increase. Is there any other effect of miller cap. 2. Does bigger plateau or smaller area indicate something? What effect will it have on previous stage and on the current stage?
Oh i got it. It is V=Q.C graph. By the way this question is irrevelant but i want to ask: If i want to drive/control gate voltage of the mosfet linearly with a constant current source externally, would it hep to linear increase in the Vgs voltage as in the case of charging a capacitor with a constant current source? @@sambenyaakov
with an opamp. there are spesific opamps to design constant current source or with a transistor+zener+resistor, you know. Good point, why they are not needed. Why they usually dont need to see a clean linear voltage rise on the gate? @@sambenyaakov
Dear Mr Ben Yaakov, Why, during the increasing of Ids the vds doesn't start decreasing at turn ON? The Vds wait Ids reaching the load current to decrease (just at the plateau Miller). Waiting for your feedback,
@@sambenyaakov yes, for example at 3.17. The vds is still constant. Why, it doesn't start decreasing when the Ids start increasing? So it's general question about the Miller effect. Thanks for your feedback,
Vds starts to decrease only after Id builds up to the inductor current. Up to that point, the inductor current is partially flowing thought the upper transistor's diode (or in general, the diode in any PWM converter topology) and thus clamping Vds to the bus voltage.
Thank you professor. I have a question maybe you can answer. In a half bridge circuit when the low side n- channel transistor is off and the gate is low via a transistor, when the high side transistor switches on the dv/dt on the drain of the low side transistor is so high it switches on the low side MOSFET for a couple of nanoseconds even with the gate connected to ground. I think this is due to feedback via Cgd. This results in high cross current or shoot through current. Is there a way to illiminate this? I now solved this by turning the p an n channel transistor around. This results in more circuitry because now I have to use a negative voltage to switch on the pfet and a Vb voltage+10V to switch the nfet. Can this be done easier with some of your expert circuit analysis? Thank your for reading my post.
A stronger low side drive for off is generally solving the problem. Another way is to use a bipolar drive. See: ua-cam.com/video/9HQsi2F01GU/v-deo.html
![Lp. Сердце Вселенной #1 НАЧАЛО ПУТЕШЕСТВИЯ [Новый сезон] • Майнкрафт](http://i.ytimg.com/vi/380Q7gLWGvk/mqdefault.jpg)
Dear Professor, thank you for your wonderful video and efforts. Greetings from Turkey..
👍🙏😊
What a wonderful explanation Prof. we are indebted!
👍😊
Dear Sam, Thank you so much for all your videos and detailed explanations. It helped me so much to deeply understand a lots of processes in electronics!!! I become a really big fan of your lectures!
Will it be possible to make a video about mosfet/igbt protections such us miller clamp and desaturation protection?
Thank you.
Thanks. Good subjects. Will try.
@@sambenyaakov Thank you so much !!!!
As always: Great video! Keep up the good work.
Thanks
Thank you for your time and for producing the videos. Could you please prepare a video on how to design and simulate a buck converter from scratch? Thank you.
Have you seen
ua-cam.com/video/HtwiIIPekfs/v-deo.html
ua-cam.com/video/1iq-YA2ivos/v-deo.html
Hello Professor! Thanks for the wonderful explanation. Im however getting stuck at one point. When you draw the small signal model using the purturbation at the gate why does the current in Coss flow from direction Source towards Drain and not the other way round. thankyou so much!
The main driving force of the Coss current is the dependent source of the MOSFET which, for a positive input, pulls the current to ground. The contribution of the gate current to Coss is negligible.
Nice presentation. I just don't get the point you mentioned at the last slide. You mentioned that the input impedance is resistive because the changes in the voltage dependent current source passes through Cgd regardless of the value of this capacitance. However, the flat region of Vgs happens only after Id already reached the load value and then the voltage is allowed to drop. To me, the change in Vds is what triggers the start of the flat region.
You are correct, but I was referring to the situation within the flat region.
Thank you for all your content!
Thanks
Professor Yaakov, i have some trouble to understand this topic on turn on. Could you please help me out.
1) In your Explanation you assume a delta Id during the VGS flat region. How is it possible to make this assumption. If i look at the characteristics of the turn on the current through the MOSFET is already Equal to the inductor current and constant during the VGS flat region. It doesnt change anymore.
2) After the miller plateau, the VGS rises until the maximum value. Why does the drain current stay constant? I understand that the drain current already reached the Max inductor current, but how do i explain it with typicall MOS equations? The drain current should rise as long as VGS rises.
3) Also again referring to Drain current equations. During the plateau VDS falls to 0. When VDS
Please try to see other related videos in my channel
To me, the previous video on gate charge was bit more intuitive.
1. Can you please explain why Cgs is no longer in the equivalent circuit?
2. Also, during the time Vds is dropping to zero, isn't Cgd being charged? It will be charged again after Vds reaches zero as well, what actually changed before and after-Only Cgs being charged additionally in the later half?
3. Is the Vgs constant due to the lower time constant (low Zin and Cgd)?
The quality of video is fabulous as usual.
Hi Maksudul, Well this video was motivation by a comment stating that the guy still did not understand why the Vgs is flat.
1. Cgs was removed to get Zin and then was put back But I have wrongly labeled it as Cgd (thanks for noticing this). I will note this in the title page of video.
3. Yes but: Zin and Cgs (in practice it doe not make any difference since in both cases the time constant is in the nsec range)
@@sambenyaakov Thanks a lot Dr. Yaakov. Would you consider making a tutorial on (1) gate driver considerations with GaN MOSFETs and (2) Conducted EMI issues while designing PCBs? There are few tutorials on how to work around, but I was looking for something more intuitive. Thanks again.
Hi Thanks for explanation. I have few questions.
1. In general, what all is the miller capacitance affecting.
Input cap of Mosfet will increase which will affect the previous driver , o/p cap will also increase. Is there any other effect of miller cap.
2. Does bigger plateau or smaller area indicate something? What effect will it have on previous stage and on the current stage?
A longer plate means that there is need for higher gate current for same rise time.
Hi, i dont understand why there is linear increase at the Vgs when apply pulse before the plateua.
Charging the input capacitances.
Oh i got it. It is V=Q.C graph. By the way this question is irrevelant but i want to ask: If i want to drive/control gate voltage of the mosfet linearly with a constant current source externally, would it hep to linear increase in the Vgs voltage as in the case of charging a capacitor with a constant current source? @@sambenyaakov
@@coderhex1675 Hoe would you build a constant current drive? Possible but really not needed.
with an opamp. there are spesific opamps to design constant current source or with a transistor+zener+resistor, you know.
Good point, why they are not needed. Why they usually dont need to see a clean linear voltage rise on the gate? @@sambenyaakov
@@coderhex1675e
what is really needed is a stepwise drive. There are some drivers that do that.
Dear Mr Ben Yaakov,
Why, during the increasing of Ids the vds doesn't start decreasing at turn ON? The Vds wait Ids reaching the load current to decrease (just at the plateau Miller).
Waiting for your feedback,
Please indicate minute n video
@@sambenyaakov yes, for example at 3.17. The vds is still constant. Why, it doesn't start decreasing when the Ids start increasing? So it's general question about the Miller effect.
Thanks for your feedback,
Vds starts to decrease only after Id builds up to the inductor current. Up to that point, the inductor current is partially flowing thought the upper transistor's diode (or in general, the diode in any PWM converter topology) and thus clamping Vds to the bus voltage.
Thank you professor. I have a question maybe you can answer. In a half bridge circuit when the low side n- channel transistor is off and the gate is low via a transistor, when the high side transistor switches on the dv/dt on the drain of the low side transistor is so high it switches on the low side MOSFET for a couple of nanoseconds even with the gate connected to ground. I think this is due to feedback via Cgd. This results in high cross current or shoot through current. Is there a way to illiminate this? I now solved this by turning the p an n channel transistor around. This results in more circuitry because now I have to use a negative voltage to switch on the pfet and a Vb voltage+10V to switch the nfet. Can this be done easier with some of your expert circuit analysis? Thank your for reading my post.
A stronger low side drive for off is generally solving the problem. Another way is to use a bipolar drive. See: ua-cam.com/video/9HQsi2F01GU/v-deo.html
@@sambenyaakov
Thank you for the reply. I have tried this but when the Fets heat up trouble starts again.
@10:30 from where this 0.1 comes in the Vgs equation?
You mean 0.14?
is it Coss = Cds?
Approximately, the Coss designation shows how it was measured. Between drain and gate shorted to source.
Sir, do you have video talk about switching loss or power loss
ua-cam.com/video/l4XxpDVoqs8/v-deo.html
ua-cam.com/video/w4cxLPl2Wsg/v-deo.html
@@sambenyaakov thanks
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