Thanks for the great video. Your videos are always a great help for students and professionals alike. However, I would like to point out a mistake in this video. At 40:57, it is said that the nonlinear effect of the capacitor would reduce the switching losses. Here, you compare two cases, one with a "constant low capacitance" and the other with "high capacitance at low Vds and low capacitance at high Vds (nonlinear C)". The increase in C will always have a higher charge requirement for increasing its terminal voltage, resulting in increased losses. I think the "red line" representing constant C should start decreasing when Vgs hits platue region, consequently dropping Vds to zero by nearly 10nC. Whereas, in the case of nonlinear capacitor, the drop in Vds would extend beyond 10nC due to the increased capacitance as you have shown. Thus, the nonlinear effect of the capacitor (increased C in lower Vds) should cause an increase in switching losses.
Thanks for comment. I am sorry, but this portion of the video is all messed up, the pointer position is off and I am afraid that my explanation was not clear. You may be right but this is a 5 years old video and it is difficult for me to go back to it. My apology.
You all prolly dont care at all but does anyone know a method to get back into an Instagram account?? I stupidly forgot the account password. I appreciate any assistance you can give me.
@Louis Kyler thanks for your reply. I found the site thru google and Im waiting for the hacking stuff atm. Looks like it's gonna take a while so I will get back to you later when my account password hopefully is recovered.
I guess the cursor in this tutorial being pointed to at, is offset by few scales depending on full screen or not :) !! But thank you very much for making this video. This was extremely informative and useful.
@@sambenyaakov I hope you are fine, Sir. I have a doubt!! I couldn't find the value of Gate inductance, however drain inductance and source inductance were given. The values of Gate and Source inductance are required to calculate the minimum required Resistance before the Gate to avoid ringing. Is there anyway to know this Gate inductance from datasheets?
Dear Professor, if you have some freetime, could you please make this lecture again? Since the cursor is shifted, one of the most important concepts of the Power Elecronics get quite hard to understand. Since your videos are quite intuitive, I almost only follow your videos. I hope my intention was clear :) In anycase, may the God bless you.
Dear professor, thank you for this lecture, which is really great, simple, but without unnecessary simplification. But I think there is one mistake. Slide 15 (time:~24min). You gave an equation for Ig1 as an average value. But after further simplification, it would be (Vt+Vgsf)/2Rg. I think the correct form of this equation should be: Ig(avg)=((Vg-Vt)+(Vg-Vp))/(2*Rg). Best regards!
It could have been really good if while explaining about the equivalent model, you could have used the pen to show the direction of currents and voltages which you were referring. I mean you could have marked the path or the nodes while you were referring it as' this current' or ' this voltage' . Anyway it was a brilliant video. Thankyou.
Dear Professor, thank you a lot for the video. I have a further question in the subject. Is it possible to help me understanding how to use and "rescale" the data sheets curves in case of different operating points? Suppose I want to use the 650 V you used in some videos at 12 V only and with a gate voltage of 5V. How should I readapt the values of the data sheets for my application?
Greetings professor. I am a fan of electronics. I've been watching your videos. I wanted to ask you about a possibility, because I had a circuit in my hands that was behaving a little strange. It basically had a load fed at 1.6v, whose current was 5A, but on the oscilloscope it had a weird oscillation. Could you consider that the oscillation was caused mainly by having a low voltage Vds in the off state in the Mosfet? I say this because if the Vds does not have great movements, then you have an increased Coss. Generally speaking, is that observation correct?
I really like this simple explanation regarding the CGD capacitance. Comparing on and off State and calculating the delta Q for the input capacitors. What really confuses me is the term miller effect and miller plateau which are used in this context across the literature. From my understanding miller effect is something related to small signal calculation (gain). It has a huge impact on my bandwidth for example in my transfer function. Interestingly this simple calculation with the total charge reveals the same miller factor, that CGD is increases by low frequency small signal gain. Is it possible to explain the miller plateau by looking at the related time constants? CGD is larger then CGS (because of Miller, additionally the FET is in saturation region since VDS>VGS-VTH), so the time constant associated with CGD should be larger. That means that when i reach the plateau the slope of charging CGD will be higher then CGS, because CGS has been already charged RELATIVLY higher.
Your assumption are wrong. Once the Vds drop to about zero the MOSFET behaves as a resistor Rds(ON). Watch again the video. Have you seen ua-cam.com/video/1XqyrAgMQVc/v-deo.html ?
Sir, the pointer is displaced. Will it be possible to rectify it sir? I am finding it difficult to understand a few points as I am a novice in this field.
Hello. It was very beneficial, thanks. but I do not understand one thing. the flat area was formed because of that feedback effect and the transistor current is linked to Vgs. when drain current heat to zero, what difference makes the feedback effect and that linkage does not work here?
yes, I mean there are videos under a specified topic, if you send me the topic and videos included, I can easily do this job. The playlist will easy the learner to learn more about specified topics you introduce. thanks for your interest. Best Regards.
Good video, thank you. I still failed to understand why vgs is flat during the linear range --I couldn't follow the explanation of what is going on during this stage that makes vgs flat.
Hi Jorge. Thanks for comment. Basically the situation is like having a "virtual ground" in an op amp. But you may be right , this should have been better explained perhps. I am contemplating a specific video on the subject of flatness. Keep your eye open for this video. If posted I will send you a link in a reply to this thread.
Hello , thanks for detailed description of MOSFET Ciss and turn on explanation that is unique. However I have some critics here. Actually I watched the minutes 9:00 till 17:00 5-6 times and could figure it out the explanation. first of all, talking about the behaviour of an electrical circuit without writing the current/voltage equation is hard to understand. maybe writing the kirchhoff's law at the nods/meshes that you want to point out could help for better clarification. secondly the mouse pointer is showing point A when you are talking about point B for example . And finally talking "current/ voltage at this point or that point" is not clear which point. maybe it is better to define the currents and voltage as Ig or Vds etc... and mention them explicitly as gate current or drain source voltage. many thanks
Hi Professor, Could you please help me by clearing my below two doubts? 1. When Vgs reaches Vth, the current Id starts to increase linearly with respect to Vgs. But during this period, Vds is high and also Vds>(Vgs-Vth), the MOSFET should operate in saturation region and hence the drain current should be increasing parabolically as per the equation Id=K(Vgs-Vth)^2..If MOSFET is operating in saturation region, then how the drain current is increasing linearly? 2. In case of R load, Vth= Plateau voltage?
I have been working with mosfets for years and I still learn things from you !
Interestingly, I myself "discovered" new angels of the subject when preparing the video
Fantastic. Thank you very much for sharing this, I found it helpful to a simulation problem I've been having just this week. Keep it up!
Thanks
I really like your videos ... It's very very resourceful for upcoming power electronic engineers.. Thanks a lot from India
Thanks for kind note.
Thanks for your hard work doing these videos.
Awesome video! Mr. Yaakov you answered so many questions of mine! Thanks!
Thanks for comment.
Thanks for your hard work. Another fantastic lecture. I am very grateful as I have learnt a lot from you!
😊
Thanks for the great video. Your videos are always a great help for students and professionals alike.
However, I would like to point out a mistake in this video. At 40:57, it is said that the nonlinear effect of the capacitor would reduce the switching losses. Here, you compare two cases, one with a "constant low capacitance" and the other with "high capacitance at low Vds and low capacitance at high Vds (nonlinear C)". The increase in C will always have a higher charge requirement for increasing its terminal voltage, resulting in increased losses. I think the "red line" representing constant C should start decreasing when Vgs hits platue region, consequently dropping Vds to zero by nearly 10nC. Whereas, in the case of nonlinear capacitor, the drop in Vds would extend beyond 10nC due to the increased capacitance as you have shown. Thus, the nonlinear effect of the capacitor (increased C in lower Vds) should cause an increase in switching losses.
Thanks for comment. I am sorry, but this portion of the video is all messed up, the pointer position is off and I am afraid that my explanation was not clear. You may be right but this is a 5 years old video and it is difficult for me to go back to it. My apology.
very detailed and comprehensive. thanks a lot.
Thanks for comment
First video on the whole UA-cam that talks about this detailed aspects of MOSFETs. Keep it up Sam !!
Thanks
You all prolly dont care at all but does anyone know a method to get back into an Instagram account??
I stupidly forgot the account password. I appreciate any assistance you can give me.
@Markus Kelvin instablaster =)
@Louis Kyler thanks for your reply. I found the site thru google and Im waiting for the hacking stuff atm.
Looks like it's gonna take a while so I will get back to you later when my account password hopefully is recovered.
@Louis Kyler it did the trick and I actually got access to my account again. I am so happy:D
Thank you so much, you saved my ass!
will watch again as i learned so much i need to think again.
thank you for detailed explanations on this topic.
Thanks.
This was very helpful lecture to under stand power mosfet.thank you so much!
😊
thank you Professor. It was interesting & helpful.
Thanks
Very interesting and very useful. Many thanks!
Thanks
great job! very thankful to you!
Thanks
The lecture was very helpful. Thanks a lot.
Thanks.
Your lectures provide a very good learning experience.
Thanks
still cannot understand it will. Thank you this is very helpful
thank you for this
thanks
Awesome. Thanks!
Thanks
Then quasiresonant and resonant topology are free from this kind of losses? Is Better when converter work with ZVS or ZCS?
I guess the cursor in this tutorial being pointed to at, is offset by few scales depending on full screen or not :) !! But thank you very much for making this video. This was extremely informative and useful.
Sorry. There was a problem with this video.
@@sambenyaakov I hope you are fine, Sir. I have a doubt!! I couldn't find the value of Gate inductance, however drain inductance and source inductance were given. The values of Gate and Source inductance are required to calculate the minimum required Resistance before the Gate to avoid ringing. Is there anyway to know this Gate inductance from datasheets?
Dear Professor, if you have some freetime, could you please make this lecture again? Since the cursor is shifted, one of the most important concepts of the Power Elecronics get quite hard to understand. Since your videos are quite intuitive, I almost only follow your videos. I hope my intention was clear :) In anycase, may the God bless you.
Thanks for good suggestion. Indeed, this is a corrupted recording. I will try.
Hi, great video with great explanation. did you happen to make an updated one with fixed cursor? 😊
Sorry this video is a blunder. I am trying to make up for it by uploading many new videos😊
Dear professor, thank you for this lecture, which is really great, simple, but without unnecessary simplification. But I think there is one mistake. Slide 15 (time:~24min). You gave an equation for Ig1 as an average value. But after further simplification, it would be (Vt+Vgsf)/2Rg. I think the correct form of this equation should be: Ig(avg)=((Vg-Vt)+(Vg-Vp))/(2*Rg).
Best regards!
It could have been really good if while explaining about the equivalent model, you could have used the pen to show the direction of currents and voltages which you were referring. I mean you could have marked the path or the nodes while you were referring it as' this current' or ' this voltage' . Anyway it was a brilliant video. Thankyou.
Good point. Will try next time.
Dear Professor, thank you a lot for the video. I have a further question in the subject. Is it possible to help me understanding how to use and "rescale" the data sheets curves in case of different operating points? Suppose I want to use the 650 V you used in some videos at 12 V only and with a gate voltage of 5V. How should I readapt the values of the data sheets for my application?
You mean the Vgs- Qg curve? Send me an email to sby@bgu.ac.il so I can send you an attachment.
Greetings professor. I am a fan of electronics. I've been watching your videos. I wanted to ask you about a possibility, because I had a circuit in my hands that was behaving a little strange. It basically had a load fed at 1.6v, whose current was 5A, but on the oscilloscope it had a weird oscillation.
Could you consider that the oscillation was caused mainly by having a low voltage Vds in the off state in the Mosfet?
I say this because if the Vds does not have great movements, then you have an increased Coss.
Generally speaking, is that observation correct?
Thanks for conversatio . Not sure that I follow the question. Please add a sketch of circuit. You can write to sby@bgu.ac.il
I really like this simple explanation regarding the CGD capacitance. Comparing on and off State and calculating the delta Q for the input capacitors. What really confuses me is the term miller effect and miller plateau which are used in this context across the literature. From my understanding miller effect is something related to small signal calculation (gain). It has a huge impact on my bandwidth for example in my transfer function. Interestingly this simple calculation with the total charge reveals the same miller factor, that CGD is increases by low frequency small signal gain.
Is it possible to explain the miller plateau by looking at the related time constants? CGD is larger then CGS (because of Miller, additionally the FET is in saturation region since VDS>VGS-VTH), so the time constant associated with CGD should be larger. That means that when i reach the plateau the slope of charging CGD will be higher then CGS, because CGS has been already charged RELATIVLY higher.
Your assumption are wrong. Once the Vds drop to about zero the MOSFET behaves as a resistor Rds(ON). Watch again the video. Have you seen ua-cam.com/video/1XqyrAgMQVc/v-deo.html ?
Sir, the pointer is displaced. Will it be possible to rectify it sir? I am finding it difficult to understand a few points as I am a novice in this field.
Sorry. I have no way to way to correct.
Hello. It was very beneficial, thanks. but I do not understand one thing. the flat area was formed because of that feedback effect and the transistor current is linked to Vgs. when drain current heat to zero, what difference makes the feedback effect and that linkage does not work here?
If the current reaches zero there is no gain so no feedback.
Very thanks for your videos, it is interesting, just the point is to make playlists of organized videos in series.
Thanks for comment. Can you help on this?
yes of course, but I need videos names organized? so I can make the playlist.
Can you get them from
ua-cam.com/users/sambenyaakovvideos
?
yes, I mean there are videos under a specified topic, if you send me the topic and videos included, I can easily do this job.
The playlist will easy the learner to learn more about specified topics you introduce.
thanks for your interest.
Best Regards.
I am putting it on my todo list
Good video, thank you. I still failed to understand why vgs is flat during the linear range --I couldn't follow the explanation of what is going on during this stage that makes vgs flat.
Hi Jorge. Thanks for comment. Basically the situation is like having a "virtual ground" in an op amp. But you may be right , this should have been better explained perhps. I am contemplating a specific video on the subject of flatness. Keep your eye open for this video. If posted I will send you a link in a reply to this thread.
ua-cam.com/video/S_o_ltLJCWY/v-deo.html I think this is the video Professor Sam mentioned just in case...
Hello , thanks for detailed description of MOSFET Ciss and turn on explanation that is unique. However I have some critics here. Actually I watched the minutes 9:00 till 17:00 5-6 times and could figure it out the explanation. first of all, talking about the behaviour of an electrical circuit without writing the current/voltage equation is hard to understand. maybe writing the kirchhoff's law at the nods/meshes that you want to point out could help for better clarification. secondly the mouse pointer is showing point A when you are talking about point B for example . And finally talking "current/ voltage at this point or that point" is not clear which point. maybe it is better to define the currents and voltage as Ig or Vds etc... and mention them explicitly as gate current or drain source voltage. many thanks
I am sorry you did not find the explanation clear. See if this can help ua-cam.com/video/of_v2N5f788/v-deo.html
Hi Professor,
Could you please help me by clearing my below two doubts?
1. When Vgs reaches Vth, the current Id starts to increase linearly with respect to Vgs. But during this period, Vds is high and also Vds>(Vgs-Vth), the MOSFET should operate in saturation region and hence the drain current should be increasing parabolically as per the equation Id=K(Vgs-Vth)^2..If MOSFET is operating in saturation region, then how the drain current is increasing linearly?
2. In case of R load, Vth= Plateau voltage?
1. The current range in power MOSFETS is at the first "linear " portion of parabolic curve.
2. For R load transition is at Vt
What is obejective of this topic...I didn't get
Never mind the objective. Did you know everything covered in this video (if you watched it)? If so you are among the few. See comment just below.
It's confusing because of the mouse pionting
Sorry. This video has indeed a pointer problem .
Sam Ben-Yaakov got it. Thank you professor.