Input Impedance Deep Dive
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- Опубліковано 17 тра 2024
- In this video, Tech Consultant Zach Peterson continues his exploration of impedance. To conclude the story of transmission line impedance, Zach explores input impedance, as well as what happens at the end of a transmission line.
0:00 Input
0:47 What is Input Impedance?
3:20 Input Impedance Formula
5:56 Termination
8:43 Examining the Input
12:23 Hyperbolic Tangent and Long Lines
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This is an absolutely amazing explanation! I remember back in the 90's when I first learned about ethernet networking, it used a bus topology. It required a terminator on each end of the bus and no one has ever been able to explain to me exactly why. The answer has always been, "that's what's required to make it work." Sure, they talked about reflections, but no one has ever been able to explain how it worked or why it had to be a particular ohm. We had different ohm terminators based on the cable we were using. Now, I understand WHY!! Thank You!!
I also have to use terminators on the NMEA 2000 bus on my boat. This bus is to connect all the sensors and multi-function displays.
Great skills you got there for explaining stuff. Keep it going!
It is very helpful! All the information you provide is very valuable!
Very clear explanation. It would be great and very interesting in the future to explain how to terminate interfaces such as LVDS, LVPECL, CML... !
Love you... very informative ❤️
Great video. Thank you! I would appreciate your extending this discussion to explore other forms of matching (e.g., using inductors and capacitors to match so as to avoid loss of power in matching resistors). I think this is what @Fred Garvin was getting at in his question/comment. - Cheers - Jim
Hi, Great Explanation. Could you please let me know what happened when we connect a small value resistor in parallel (i.e. 100Ohm) to the RS485 Bus end. Does this may effect our data transmitting?
my head is spinning ..😵💫😵💫
this is an absolutely amazing explanation!tnx sir
So nice of you
Great video! It explains the concepts really well as apposed to just writing 100s of equations haha. I have one question though, when designing a PCB where a microcontroller communicates with a device using SPI or I2C, should I use terminate the lines at the load side like you say? I've been warned multiple times about ensuring all the lines are the same length to ensure that signals reach the load at the same time, but should each line have a parallel impedance matching termination as well? Or is this something that is built on-die for the source and load?
It depends on the rise time for signals on the bus and the length of the bus. As I've noted in a different video, it has nothing to do with the clock rate. This is a common misconception; pay attention to the rise time and not the clock frequency. With SPI or I2C, you will most likely not need to terminate unless you get to really fast rise times.
In I2C, technically the lines are terminated as soon as you connect them to the Vcc rail with pull up resistors. So no they aren't terminated on-die (I've never seen it anyways). The bus capacitance and the pull-up resistors will determine the rise/fall time. I2C is an open-drain bus, so it pulls lines low by discharging the entire bus into the driver's ground. So if you have a physically smaller bus (thinner traces, shorter lines), then you will have faster rise time. You'll most likely only need to worry about termination with a backplane-sized board, and only at the High Speed standard. For example, just using the rough propagation delay value of 6 inch/ns for a minimum rise time of 15 ns in high speed mode, the signal would travel at least 90 inches during its rise time. Taking a 10% conservative limit for this signal would give a critical length of 9 inches. So it does matter with high speeds on a larger board, or possibly if you're routing through a cable and onto another board simply because you create such a long link. There is also the matter of setting the right value for any series resistor should it be needed, take a look at Fig. 46 in the I2C specification for a graph that shows maximum series resistor values vs. pull up resistor: www.pololu.com/file/0J435/UM10204.pdf
With SPI, it's a bit different. SPI is push-pull, so power is not being drawn through a pull-up resistor, and the rise time is dominated by the external capacitance + any series resistance and driver output impedance. The SPI spec on your MCU/FPGA or whatever might give a specific rise time for a specific current draw into the bus for a specific total capacitance (maybe 50 or 100 pF). For the SPI bus on a PIC32 MCU, the output transition time is specified as 5 ns for an external capacitance of 50 pF. So if we drop to 10 pF, we would expect the rise time to drop to 1 ns for a given current output and voltage level. In that case, you now have 0.6 inch length allowance (rough approximation with a very conservative 10% limit on unmatched lengths).
100 th like by me....nice explanation 🤩
Thanks for liking
Hi Zach, a question because when I am creating a pcb in only two layers and in the layer Stack Manager I want to use the bottom layer as a plane, the Altium program does not give me that option, it only lets me use the layer as a signal, so when I create a pcb with controlled impedance, the layer Stack Manager generates the correct thickness of the track and in the design rules I configure it to accept that width, but then when I run the signal integrity analysis and search the details of the track I get the impedance with 300 ohms, sometimes more, sometimes less, but when I create the pcb with 4 layers then the impedance does correspond to the calculation. Can you help me about it? Thanks in advance.
Unfortunately you cannot do a 2-layer board with a plane layer on one side. The signal integrity tool requires a plane layer to set the ground reference, otherwise the tool will return a very large value as it does not recognize pour as a reference layer. The same rule applies in higher layer count boards.
I have designed some boards where the customer added different value resistors to different signals , like at one signal they used 200 ohms to ground and on another signal they used 240 ohm. I cant understand why they had to use different value resistors if the 50 ohm trace width was same for all signals. Also they call it ODPR signals but the resistors were added externally on the board. Could you please explain this a little? Thanks.
As much as I would like to speculate, I wouldn't want to state a reason without looking at the design.
If you want to send me something to look at directly, you can email us at youtube@altium.com
hey, I got a tricky question: what should u do if Source if HIGH impedance and load is low? I have had that question for students and also we had to deal with that problem with very specific IC once upon a time. Also trans-impedance AMPs are interesting thing.
In that case, reverse the terminations, so some kind of parallel termination at the source and series termination at the end. Series is to increase a low impedance to a target value, and parallel is to decrease a high impedance to a target value.
I've never seen that type of thing except for like specialty analog stuff. Everyone usually posts guides with series termination at the source and parallel termination at the end because CMOS buffers will have low output impedance and high input impedance.
if your load high a 1Mohm resistance and you add in a 50ohm parallel to that load at the end of the transmission line won't most of the signal and current flow through the 50ohm resistance since it is much smaller? how would you get much power to load if you give the electricity such an easy path to take instead?
I am thinking in terms of a radio transmission line and an antenna for the load.
Thank you! You really answer my question about termination!
But, I have question here. Does the characteristic impedance(Z0) literally dissipate the power?
Here is the scenario
Assuming a 1.8V voltage source, and Rs, Z0, RL all 50 ohm, what happens on RL? 0.9V or 0.6V?
Appreciate in advance
In a lossless transmission line that has zero DC resistance, no radiation, and no dielectric losses, the impedance does not dissipate power. In reality, there are always these losses, so some power is lost along the transmission line. When you look at Rs, you typically do not worry about the power dissipation across the source impedance,the signal level is just specified as the value that is injected onto the transmission line. This is why the transfer function for a source terminated interconnect will omit the factor 2 in the numerator. If you just consider the propagation along a long line at a specific point before there are any reflections or received noise, then the impedance is the ratio of the voltage solution to the current solution (both obtained from the Telegrapher's equations).
@@Zachariah-Peterson Hi Zach, Thanks for prompt reply. Appreciate so much. These days I spent some time on your videos and the articles on singal integrity fundamental concept. It really helps. Thanks again.
So, as far as I known, may I suggest that, in the lossless condition, Zo is just the relationship of voltage wave over current wave; it doesn't incur any voltage drop while signal propagates over it.
As for "power dissipation across the source impedance,the signal level ..." you mentioned above, actually I don't fully get what you said. May I interpret that , at the joint point which connects source impedance and the transmission line, the only thing to do is just obey the input impedance formula and the voltage divider here; thus deriveing the voltage value that we want?
Appreciate so much!
Ray
@@user-fe5oq8bj2i Yes that is a good way to think of it, as ratios. For the source impedance, the typical model is to just put a resistor there. That means that, if you calculate the transfer function across the line with the source impedance included, you would lose half the voltage from the switching element as it gets dissipated across the source impedance. However, when the thing is actually packaged and you measure the signal level, you never see what happens between the switching element and the source impedance. The signal you get has already transitioned into your instrument and it outputs whatever value you measure on your scope. So conceptually, that means it's already felt the effects of whatever the input impedance is at that port. Since input impedance relies on working backwards from the load, you just start at the load and work backwards until you get to the driver pin, and that's basically it. You can account for the source impedance if you want to, but then it gets more complicated and is not really needed. Also, not all source impedances are purely resistive (either as a series resistor or divider or whatever other circuit). Some RF interfaces use a balun to couple signal to the output, so that gives a very specific impedance at the interface's operating frequency.
@@Zachariah-Peterson Hi Zach, thanks for detailed explanation. Appreciate it so much. So what you mean is that when the thing is packaged, it is normally built in an on-die source resistance. So we can feel free to neglect the above derivation that happens in source element and impedance. I just believe what actually display on the oscillscope, is that right?
Since based on my experience on SPECTRE simulation, the NPORT element provided on the "analogLib" will deliberately twice the amplitude of voltage level so that while the impedance between source impedance and input impedance is matched, the voltage vlaue is exactly what you specfied.
Therefore I wonder that if the instrument such as AWG have the same mechanism as the NPORT does? so we can get the voltage value that we set on the instrument while impedance is matched.
Thanks in advance
Ray
What if Zsource = Zin but ZL != Z0, will we have 0 reflection at the interface of the input with the line and we'll have a reflection at the interface of the line with the load ?
Yes you would have a reflection at the load end, so the power that transfers into the load may be less than 100%.
I dont fully comprehend why we need to understand Zin formula for digital design if we will not use this formula.
My guess is digital signal is composed of infinite sinusodial signal (fourier transformation) and that is the reason we cannot calculate infinite amount of gamma for each sinusodial wave and plug that gamma to Zin formula.
Is my point correct? If not please tell me why?
By the way, sorry for my bad english. I hope you assist me.
In digital design the point of input impedance would be two-fold: trying to model the bandwidth for flat impedance when there is a capacitive load and you've applied impedance matching, or when trying to see the minimum length at which you need to impedance match given the known impedance of your current transmission line design. If designers are trying to get around designing their single-ended protocols to 50 Ohms, then they will be doing the 2nd thing I listed here. Everyone says "25% rise time" or "1/3 rise time" but those numbers depend on the impedance of the line and the load together. For example, 65 Ohm lines will have a different rise time limit than a 35 Ohm line for a given +/-5% input impedance tolerance. To do this, you have to look at a bandwidth limit in the signal and use that bandwidth limit + your transmission line impedance to determine when the input impedance exhibits too much deviation from the load impedance. The bandwidth limit is also a bit arbitrary, you could use Nyquist, or 5th harmonic, or 7th harmonic, or the knee frequency (0.35/rise time). The knee frequency is popular because the input parasitics on a transmission line act like a 1st order filter, and 0.35/rise time would be the minimum measurement bandwidth needed to reproduce that signal without Gibbs artefacts, but it's important to note that this is something that was taken from oscilloscope measurement techniques.
How long should a TL be to be considered long?
Hi vol vox,
It depends on a few factors. For a really rough approximation, you can use the rise time of the signal. If a trace length is about 25% or less than the distance a digital signal will travel between the source and load, then the source basically doesn't "see" the transmission line and only interacts with the load. This isn't entirely true, it's just a rough approximation. What it tells you though, is that protocols like I2C or SPI are generally slow enough to where they don't need to worry about long interconnects unless you are sending signals board-to-board, or unless you have a very large board, and now you have a very long interconnect and it might be important.
The best way to do it is to use some top-end of the signal bandwidth and check based on that. This is where it gets tricky for digital because a digital signal has its power spread out over a huge range of frequencies, so which do you pick? I'll do a video that walks you through this as it's a really common question.
For an analog signal, you can calculate the propagation constant for the analog frequency and use it directly in the input impedance equation.
For more about this, you can read a blog on Altium's website: resources.altium.com/p/why-there-transmission-line-critical-length