FPGAs and low latency trading - Williston Hayes - Optiver - FPL2020

On 2 September 2020 Optiver presented at FPL2020 - 30th International Conference on Field-Programmable Logic and Applications on how we leverage FPGA technology for low latency trading purposes.
Williston gives an overview of the environment in which we operate so that you may better understand how trading and FPGAs intersect. By using examples of system implementations, as well as describing the building blocks of a simple trading system, you will walk away with a better idea of how valuable FPGAs are in the low latency trading space. In addition, our domain forces us to make design decisions and implementation choices that wouldn't normally be used in a traditional FPGA application, making it all the more interesting.

[@AshishPatel-vy7mn]

Wish, I had found this earlier. I have been working on FPGA's and ASIC's since I started my career. Since last few years I have been trying to switch career into trading, especially algo trading. It's great to see FPGA at the core of HFT.

[@TheDonMan97]

Thank you for this! I was often confused about where the latency happened in software applications and your presentation made me understand where it happens.

[@alexp10000]

Very well-structured and cogent. Thank you

[@Adil-sm3yz]

this is really cool, people often talk about FPGA's but this presentation was a great intro into how it can be used beneficially in the real world
great presentation!

[@SanjeevkumarMSnj]

This is one the top presentation on low latency trading systems.. thanks a lot

[@blazkowicz666]

Could you link me to some more resources? A Google search yielded very sparse information. Thanks

[@SkiddingMonster]

One other application where latency is extremely important is Trigger systems for high-energy collider physics experiments, like LHC in CERN. So hearing you say that standard Xilinx IPs aren't designed for optimal latency hits very close to home

[@blazkowicz666]

Do you use gRPC? How do you handle Head of Line blocking, especially when a latency penalty is heavy?

[@amirebrahimi8107]

Thank you guys. What a presentation! May I ask which FPGA and interactive broker do you use?

[@larsolsson571]

No broker, direct access to the exchange

[@allansh828]

can you do it with DPU?

[@onceappuonatime]

When I get to meet Williston, I want to ask him why haven't they designed an ASIC for trading yet? given that his team has had so much experience with FPGAs.

[@Intrafuseproductions]

FGPAs are reprogrammable, so as new trading/execution logic is developed, it can be "deployed" to the FPGA. An ASIC has one set of logic that you can't modify, meaning you'd need to replace the device each time.

[@AshishPatel-vy7mn]

@@Intrafuseproductions Also, market behaviours keep changing over a period of time. You will always need to reconfigure your strategies over time. No single strategy will always give same results.

[@alexfloresq9003]

Here for ES3F1 👽👽👽👽

[@bravosierra2010]

What tools do use for testing?

[@uanbu6539]

So essentially you're saying c++ is no longer relevant here because the message doesn't even reach the software layer.

[@uanbu6539]

@@vimusa2440 do you have a link please?