Numerical on set associative mapping in Cache Memory |set associative mapping

[@_Shash_Music]

legend oh sir app ❤ apke channel se padh ke ache marks score kiye ! thank you so much sir ! will recommend the upcoming juniors for COA

[@aradhyaagrawal6632]

Thanks for clearing all my doubts sir... : )

[@harshnarayan2601]

Very helpful vdio sir

[@Adarsh.24]

But sir word size of cache memory to given hai 2048 to vhi kyu nhi rkh skte at 16:45 ?

[@ik_2026]

Right....aktu students ho kya 😅😅

[@thakurpresents8272]

NICE EXPLANATION SIR ❤❤

[@mr.unknown0815]

Awesome 😎

[@bibekrawat4008]

Sir I have one question:
Consider a system with 4 way associative cache of 256 kb. The cache line is 8 words (32 bits per word). The smallest addressable unit is a byte and memory bits are 64 bit long.
a) How many bits are used for tag and index field of cache mapping?
b) What memory address can make to set 289 of the cache?

[@kumkumslab5811]

ab to passout ho gae hoge

[@aakashnishad7048]

Thanks sir

[@pritamsarkar3371]

2048 words or 128K will be the size of the cache, and extra 7K extra overhead directory space needed due to tag bits per each block/line

[@LSAcademy007]

Kindly clear your concept again and check the solution of same problem over internet from otherw website.or send me your email id ,I will send you solution manual provided by Morris Mano

[@pritamsarkar3371]

@@LSAcademy007 ok, sir this means, the extra tag bits are also stored in the same cache, thank u sir

[@shifamirza2672]

Sir isme no of main memory block to 32 honge na aapne itne kyu liye h plss sir reply krdiye pls sir🙏

[@sayanidas_7337]

sir ...it is already mentioned in the question that cache has 2048 words but still at the end you calculated no. of cache words by 2 to the power index bits i.e,2^10=1024 .... how is it possible ?

[@LSAcademy007]

Since set size is 2, so each location of cache memory have 2 memory words(tag1+data1+tag2+data2=78 )and cache size indicates 1024 locations with each location of cache has 2 memory words of width 78 bits. still feel doubt, contact me on [e-mail] for clarification.....

[@sayanidas_7337]

@@LSAcademy007 .
Then if it is 4 way set associative cache... The size of the cache would be (2048/4)=512 words . Is it alright?

[@LSAcademy007]

Yes, then cache memory size will be 512*176 i.e. 512 words with each word havíng 176 bits(tag1+data1+tag2+data2+tag3+data3+tag4+data4)

[@sayanidas_7337]

@@LSAcademy007 thanks a lot sir

[@fin807]

Sir cache m/m size is already given in ques i.e 2048 x 32 yet we find the answer by adding the tag as 1024 x 78
Why are tag bits added 2 times i.e in main m/m address and word address also

[@raka007]

your concept is not clear
tag is added 2 time because its 2 way set associate mapping
so cache memory will conatain tag + data 2 times

[@VivekGupta-xb5md]

Sir you have told size of each wor d is 32 bit. And each block contain 4word. So the total size of block should be 32*4=128bit. So 32 block size? How?

[@LSAcademy007]

Block contains words .word length is 32 bit. If block has 4 words then, then length of each word in the block will still be 32 bit..if u need further clarification,send your query on [e-mail]

[@VivekGupta-xb5md]

@@LSAcademy007 sir I have a doubt with a question by applying your theory...
Question is sensed to your Gmail please goes through sir...